GigaDevice partners with SEGGER on Embedded Studio for <span style='color:red'>RISC-V</span>
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GigaDevice partners with SEGGER on Embedded Studio for RISC-V

　　GigaDevice and SEGGER jointly announced today that GigaDevice's customers can now use SEGGER's leading multi-platform IDE Embedded Studio free of charge across all GigaDevice RISC-V microcontrollers (MCUs) including the latest GD32VW553.　　GigaDevice officially launched the world's first RISC-V based GD32VF103 series of 32-bit general-purpose MCU products in 2019, and very recently introduced the dual-band wireless GD32VW553 series, based on a 160MHz RISC-V core. The device is equipped with 4MB of flash and 320KB of SRAM. GD32VW553 supports the latest Wi-Fi 6 and BLE 5.2 wireless communication protocols. It also integrates rich peripheral interfaces and hardware encryption functions to create a safe and reliable wireless connection solution. High performance and low energy consumption make it ideal for smart home appliances, industrial Internet, communication gateway and other wireless connection scenarios.　　Characterized by its flexibility of use, Embedded Studio has all the tools and features a developer needs for professional embedded C and C++ development, including a complete toolchain, optimized run-time library, core simulator and hardware debugging with the J-Link debug probes. Other SEGGER tools that also fully support GD32V RISC-V MCUs include: The market-leading J-Link debug probe, Ozone debugger, real-time operating system embOS and software libraries for communications, data storage, compression, and IoT, as well as the Flasher family of in-circuit programmers.　　“GigaDevice and SEGGER have a long history of cooperation”, says Eric Jin, GigaDevice's Product Marketing Director. “SEGGER was the first ecosystem partner to support the GD32V RISC-V core MCUs. Making SEGGER Embedded Studio available to our customers free of charge facilitates software development for our GD32V series. Embedded Studio fully supports and adapts to the GD32V family of RISC-V MCUs in terms of efficiency, performance, and ease of use, significantly accelerating the development and mass production of innovative applications.”　　“We have been partners with GigaDevice and have supported GigaDevice products for many years now,“ says Ivo Geilenbruegge, Managing Director of SEGGER. “We immediately added full tool support when they unveiled the first commercially available flash-based RISC-V microcontroller back in 2019. We are impressed by their speed of innovation, the many new devices they have brought to market, and the extent to which they’ve quickly become a key player in the industry.”　　For user registration and downloads, visit wiki.segger.com/GD32V now to get Embedded Studio available free of charge for commercial development on GD32V MCUs.　　About GigaDevice　　GigaDevice Semiconductor Inc. (SSE Stock Code 603986) is a global leading fabless supplier. The company was founded in April 2005 and headquartered in Beijing, China, with branch offices in many countries and regions worldwide, providing local support at customers' fingertips. Committed to building a complete ecosystem with four major product lines – Flash memory, MCU, sensor and analog – as the core driving force, GigaDevice can provide a wide range of solutions and services in the fields of industrial, automotive, computing, consumer electronics, IoT, mobile, networking and communications. GigaDevice has received the ISO26262:2018 automotive functional safety ASIL D certification, as well as ISO9001, ISO14001, ISO45001, and Duns certifications. In a constant quest to expand our technology offering to customers, GigaDevice has also formed strategic alliances with leading foundries, assembly, and test plants to streamline supply chain management. For more details, please visit: www.gigadevice.com.　　About SEGGER　　SEGGER Microcontroller, now in its fourth decade in the embedded system industry, produces cutting-edge RTOS and Software Libraries, the marketing-leading J-Link and J-Trace debug and trace probes, a fast, robust, reliable, and easy-to-use family of Flasher In-System Programmers and second-to-none software development tools.　　SEGGER's all-in-one solution emPower OS provides an RTOS plus a complete spectrum of software libraries including communication, security, data compression and storage, user interface software and more. Using emPower OS gives developers a head start, benefiting from decades of experience in the industry.　　SEGGER's professional embedded development software and tools are simple in design, optimized for embedded systems, and support the entire embedded system development process through affordable, high-quality, flexible, and easy-to-use tools.　　The company was founded by Rolf Segger in 1992, is privately held, and is growing steadily. SEGGER also has a U.S. office in the Boston area and branch operations in Silicon Valley, Shanghai, and the UK, plus distributors on most continents, making SEGGER’s full product range available worldwide.
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Release time：2024-01-02 16:39 reading：2233 Continue reading>>
Renesas Unveils the First Generation of Own 32-bit <span style='color:red'>RISC-V</span> CPU Core Ahead of Competition
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Renesas Unveils the First Generation of Own 32-bit RISC-V CPU Core Ahead of Competition

　　TOKYO, Japan ― Renesas Electronics Corporation (TSE:6723), a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas’ existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm® Cortex®-M architecture.　　RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.　　“Renesas takes pride in offering embedded processing solutions for the broadest range of customers and applications,” said Daryl Khoo, Vice President of the IoT Platform Division at Renesas. “This new core extends our leadership in the RISC-V market and uniquely positions us to deliver more solutions that accommodate a diverse range of requirements.”　　“We congratulate Renesas on achieving its recent milestone in 32-bit RISC-V MCU architecture development,” said Calista Redmond, CEO at RISC-V International. “This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market.”　　The Renesas RISC-V CPU achieves an impressive 3.27 CoreMark/MHz performance, outperforming similar architectures on the market. It includes extensions to improve performance, while reducing code size.　　Renesas is sampling devices based on the new core to select customers, with plans to launch its first RISC-V-based MCU and associated development tools in Q1 2024. Details of the new MCU will be published at that time. More information about RISC-V solutions is available at: renesas.com/risc-v. A blog article about the new RISC-V CPU is available here.　　Renesas MCU Leadership　　The world leader in MCUs, Renesas ships more than 3.5 billion units per year, with approximately 50% of shipments serving the automotive industry, and the remainder supporting industrial and Internet of Things applications as well as data center and communications infrastructure. Renesas has the broadest portfolio of 8-, 16- and 32-bit devices, delivering unmatched quality and efficiency with exceptional performance. As a trusted supplier, Renesas has decades of experience designing smart, secure MCUs, backed by a dual-source production model, the industry’s most advanced MCU process technology and a vast network of more than 200 ecosystem partners.　　About Renesas Electronics Corporation　　Renesas Electronics Corporation (TSE: 6723) empowers a safer, smarter and more sustainable future where technology helps make our lives easier. The leading global provider of microcontrollers, Renesas combines our expertise in embedded processing, analog, power and connectivity to deliver complete semiconductor solutions. These Winning Combinations accelerate time to market for automotive, industrial, infrastructure and IoT applications, enabling billions of connected, intelligent devices that enhance the way people work and live.　　Follow us on LinkedIn, Facebook, X, YouTube, and Instagram.　　(Remarks) Arm, Arm Cortex are trademarks or registered trademarks of Arm Limited in the EU and other countries. All names of products or services mentioned in this press release are trademarks or registered trademarks of their respective owners.
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Release time：2023-12-08 17:06 reading：2393 Continue reading>>
<span style='color:red'>RISC-V</span> Summit 2022: All Your CPUs Belong to Us
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RISC-V Summit 2022: All Your CPUs Belong to Us

　　In a recent guest editorial here on EE Times, legendary professor David Patterson wrote about busting the five myths around the RISC-V instruction set architecture (ISA). At the recent RISC-V Summit organized by RISC-V International, the consortium that manages and promotes the RISC-V Instruction Set Architecture (ISA), its president, Calista Redmond, had a far more blunt message: RISC-V is inevitable.　　In fact, she said, RISC-V will eventually have the best CPUs, the best software running on them and the best ecosystem of any microprocessor core family. These are mighty strong words for a nascent ISA that is only about 10 years old and that competes with the far more established Arm and x86 ISAs. It almost sounded like the Borg from Star Trek when they say, “Resistance is futile.”　　RISC-V International CEO Calista Redmond (Source: RISC-V International)　　Redmond’s reason for saying that RISC-V is inevitable is that its growth and success are built upon shared investments of many companies, universities and contributors. RISC-V International has more than 3180 members. Billions of dollars have been invested in the architecture, including national programs from countries and regions such as India and the E.U. This enables the development of the “best” processor in multiple price and performance categories with the contributions of so many ideas and collective knowledge. Because RISC-V is scalable, customizable and modular, it can easily be optimized for different workloads and applications.　　The software ecosystem is growing, and efforts are underway to make software development more efficient with profiles and standards like a single hypervisor standard.　　RISC-V origins　　RISC-V is an open specification like Ethernet. It was developed at University of California, Berkeley (UC Berkeley) with a clean-slate approach to RISC (reduced instruction set computer) designs. There had been many RISC ISAs in the past: 29K, Alpha, Arm, i960, MIPS, PowerPC and SPARC to name some. All those other RISC architectures have been tied to a corporate owner, and most have become outdated.　　The researchers at UC Berkley felt it was time for a clean slate with no corporate owners, initially for educational use, but they soon recognized it was useful for more than instructional purposes.　　With this approach, multiple companies can build CPUs using the open standard. This means that there are many different options to get RISC-V CPUs, and there are more every year. You can download the specifications and design your own CPU. You can download open-source versions of RISC-V CPUs. You can buy a CPU core from multiple IP vendors. You can get a customized CPU core from other vendors. You can buy chiplets with RISC-V cores. You can buy a chip with an RISC-V processor. Or you can buy a full AI chip running with RISC-V cores.
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Release time：2023-01-04 13:06 reading：1948 Continue reading>>
SiFive announces first open-source <span style='color:red'>RISC-V</span>-based SoC platform with NVIDIA Deep Learning Accelerator technology
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SiFive announces first open-source RISC-V-based SoC platform with NVIDIA Deep Learning Accelerator technology

SiFive, a provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA’s Deep Learning Accelerator (NVDLA) technology.The demo will be shown this week at the Hot Chips conference and consists of NVDLA running on an FPGA connected via ChipLink to SiFive’s HiFive Unleashed board powered by the Freedom U540, the world’s first Linux-capable RISC-V processor. The complete SiFive implementation is well suited for intelligence at the edge, where high-performance with improved power and area profiles are crucial. SiFive’s silicon design capabilities and innovative business model enables a simplified path to building custom silicon on the RISC-V architecture with NVDLA.NVIDIA open-sourced its leading deep learning accelerator over a year ago to spark the creation of more AI silicon solutions. Open-source architectures such as NVDLA and RISC-V are essential building blocks of innovation for Big Data and AI solutions.“It is great to see open-source collaborations, where leading technologies such as NVDLA can make the way for more custom silicon to enhance the applications that require inference engines and accelerators,” said Yunsup Lee, co-founder and CTO, SiFive. “This is exactly how companies can extend the reach of their platforms.”“NVIDIA open sourced its NVDLA architecture to drive the adoption of AI,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. “Our collaboration with SiFive enables customized AI silicon solutions for emerging applications and markets where the combination of RISC-V and NVDLA will be very attractive.”
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Release time：2018-08-21 00:00 reading：1250 Continue reading>>
Rambus Taps <span style='color:red'>RISC-V</span> for Root of Trust
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Rambus Taps RISC-V for Root of Trust

　　Rambus announced a security block based on the RISC-V core aimed, in part, to plug the Meltdown/Spectre flawsrevealed earlier this year. The CryptoManager Root of Trust targets use in a wide spectrum of ASICs, microcontrollers, and SoCs in embedded systems.　　Rambus claims that the new block sports several advantages over root-of-trust functions already integrated in most existing embedded processors. It suggested that OEMs should move this fundamental hardware-security function out of mainstream x86 and ARM embedded processors that Spectre/Meltdown showed are vulnerable to side-channel attacks.　　However, an NXP security expert said that the root-of-trust function ideally should be implemented in a standalone chip, a practice that high-security systems use. The trend of integrating the function into larger chips helped save costs, but it was a step backward in security, said Sami Nassar, vice president of cybersecurity solutions at NXP Semiconductors.　　“The security execution environment and the root of trust should be outside the main processor … you don’t want to mix security and general processing,” he said. “It’s not complicated to [isolate the two], and it doesn’t add much cost, but people cut corners, and it’s proven to be a weak model.”　　Rambus argues that its block lets designers at least move the key security functions off of embedded processors that often use speculative execution. Spectre/Meltdown showed that the popular performance-boosting function can leave secure data exposed in caches.　　Nassar countered that highly secure systems generally use standalone root-of-trust chips separately from host processors. Integrated chips are more vulnerable because they share I/O and cache blocks, he said.　　The first mainstream implementations of hardware root-of-trust security defined by the Trusted Computing Group nearly 15 years ago were standalone chips called secure modules. However, over time, major processor and IP vendors such as Intel and ARM subsumed those functions in their chips.　　The big processor and IP vendors argued that their implementations kept secure and open paths separate inside a chip. However, the Spectre/Meltdown attacks showed that the complexity of today’s devices leave room for vulnerabilities that are sometimes not found for years.　　Rambus and others argue that the new block and the RISC-V core that it is based on have advantages over transitional implementations of a root of trust.　　For example, the CryptoManager supports multiple roots, letting processes use the core without exposing keys or secrets to other processes. The Rambus core is fully programmable and sports new levels of protection against side-channel attacks, emulation, reverse-engineering, and other hacks.　　A Rambus security expert was one of the researchers behind the initial papers on Spectre/Meltdown. The company announced last year that it would adopt a RISC-V core from startup SiFive for use in security applications.　　After some initial hiccups, Intel said in March that it now has firmware available to mitigate Spectre/Meltdown flaws in its processors as much as nine years old. It promised that changes in hardware to plug the flaws will emerge in new Xeon and Core chips starting in the second half of this year.　　“The semiconductor industry faced some of its biggest security issues this year with recent vulnerabilities, and the potential to encounter additional security flaws will not go away any time soon as more IoT devices enter the market,” said Abhi Dugar, an IoT security analyst for International Data Corp., speaking in a Rambus press release.　　“To address existing and new threats, establishing trust at the hardware level will be critical, and a secure siloed core can help ensure that this new generation of devices can be protected from security flaws.”
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Release time：2018-04-17 00:00 reading：1195 Continue reading>>
SiFive Preps <span style='color:red'>RISC-V</span> Cloud Service
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SiFive Preps RISC-V Cloud Service

　　SiFive will try to build an easier, cheaper, faster way to design chips with a new $50.6 million funding round that included Huami, the venture arm of China’s Xiaomi. The series C aims to bring the startup to profitability and establish a broad market for its RISC-V cores.　　SiFive will release a cloud service for designing RISC-V cores this year. It will expand it into an SoC design platform next year with silicon blocks from partners, said Naveed Sherwani, an industry veteran named chief executive of SiFive last July after 10 years at Open Silicon.　　At an event announcing the funding, Sherwani made several ambitious promises he said would amount to a revolution in SoC design.　　“Today it takes 9-18 months to finish a chip. In 12-18 months we will release a system that takes besides the two-month’s fab time, just 15-20 days… today people take 30 days to validate RTL, but we will do it in less than 3-5 hours — this is my promise,” he said.　　In addition, SiFive’s IP partners will provide blocks at low or no cost until an SoC is in production. Upfront charges for IP can amount to 35 percent of the cost of prototyping an SoC, as much as $5 million in some cases. SiFive aims to reduce those costs as much as 85 percent so users can prototype a chip for roughly $750,000, said Shafy Eltoukhy, who oversees SiFive’s partner program.　　“Anyone with a Web interface will be able to design amazing chips and solve problems in their communities,” said Sherwani, vowing to make the service free for universities and developing countries.　　Some of SiFive’s promises are “very ambitious,” said market watcher Linley Gwennap of the Linley Group. Speeding up the design process is good, but it doesn’t add differentiation, “so the value of this approach is unclear. Most SoC startups design the most crucial IP blocks on their chips to ensure differentiation,” he said.　　Although SiFive may reduce upfront costs, “customers still have to pay for the IP later when they ship product, so the program doesn’t reduce IP cost, it just delays it,” he added.　　It’s not yet clear where SiFive’s platform will get traction. The service could give the emerging class of crowdfunded hardware startups an alternative to using off-the-shelf chips. Existing chip designers might find the service useful in lowering costs for SoCs that don’t require custom features.　　To date, a handful of established electronics companies such as Microsemi, Nvidia and Western Digital are adopting RISC-V. They see the free instruction set architecture and its growing set of open source implementations as a way to reduce costs of designing their own cores.　　Startup Esperanto Technologies announced last fall it is developing a family of high-end processors with RISC-V. And Andes Technology is embracing RISC-V as an alternative to its proprietary cores.　　The new funding round was a large one for SiFive. The company,founded in July 2016 by a team of Berkeley grad students and their advisor who designed the initial RISC-V cores, had raised $13.8 million to date.　　Investors were led in the latest round by Chenwei, a China VC firm with a broad tech portfolio that includes investments with Sutter Hill Ventures, SiFve’s initial lead investor. Other new investors included SK Telecom, Huami, two unnamed semiconductor companies and Western Digital, an existing RISC-V user.　　“A lot of the RISC-V revolution will happen in China and India,” said Stefan Dyckerhoff, a managing director at Sutter Hill Ventures.　　Sherwani said the funds will help him double his team to about 100 people, hiring mainly engineers with a combination of silicon and software expertise. It will also pay for about a dozen tape outs he wants to do this year to verify partner IP.　　The SiFive cloud service he aims to build will let users create SoCs by selecting pre-verified RISC-V cores and peripheral IP blocks. It will generate fab-ready files, generally shielding customers from the complex details of EDA flows.　　The service also will support an app store of tools from SiFive and its partners. A basic version of the service for designing RISC-V cores could be available as early as September.　　SiFive’s IP partner program, launched in August, includes a dozen generally small IP companies so far and is adding a new member about every two weeks.　　They include Analog Bits, Dover Microsystems, FlexLogix, Rambus and UltraSoC. DSPs are among the holes it has yet to fill.　　Much of SiFive’s work behind the scenes will be in creating templates for each block, building subsystems of multiple blocks and making sure each combination of blocks can work together.　　Meanwhile the company is already logging revenues from licenses for a handful of RISC-V cores it has designed to date. SiFive’s first purchase order was issued in mid-2016 for a soft core that acts as a cache coherent block in a Microsemi design.　　“This week we received a multimillion-dollar order for the program that uses that processor from SiFive,” said Ted Speers, a Microsemi fellow and a board member of the RISC-V Foundation.　　Some see RISC-V upending the dominance of Intel and Arm in microprocessors. At a RISC-V event last fall, WD said it will standardize on RISC-V and someday ship as many as two billion cores a year embedded in its disk and solid-state drives.　　“Based on how Linux went from enthusiast users to a major OS for the data center, I predict in 10 years we will see every data center processor and half of edge device processors use RISC-V. All the control points will be broken, so you can build an SoC any way you want, with any interfaces you want— this is the freedom RISC-V will bring by 2028,” said Zvonimir Bandic, a senior director at WD and a board member of the RISC-V Foundation.　　“I’m concerned that the talk of RISC-V eventually dominating the data center and client computing distracts from the hard work that needs to be done in the interim,” said analyst Gwennap. “So far, RISC-V has been adopted only for deeply embedded cores and not for running application software,” he added.　　While others such as Esperanto will go head-to-head with giants such as Intel, that is clearly not SiFive’s goal.　　Some developers have been keen to get their hands on SiFive’s latest processor, because it is the first RISC-V chip capable of running Linux. At the event last week, the company did not even mention it had just shipped a few cases worth of developer cards with the chips.
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Release time：2018-04-03 00:00 reading：1148 Continue reading>>
<span style='color:red'>RISC-V</span> Spins into Drives, AI
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RISC-V Spins into Drives, AI

　　Storage giant Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture. The two moves suggest that RISC-V has emerged as a viable — but not yet mature — alternative to ARM and the x86.　　Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.　　For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.A 16-core “ET-Maxion” targeting highest single-thread performanceA 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.　　“Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem, and having a startup try to take it to high-end products is a big deal because to date, RISC-V has been mainly in low-end microcontrollers for the IoT,” said Linley Gwennap, principal of market watcher The Linley Group.　　Esperanto has kept a tight lid on its plans to date, although its chief executive, microprocessor veteran David Ditzel, has been a fixture at RISC-V events for some time. Ditzel designed server processors at the former Sun Microsystems and startup Transmeta before doing a relatively short stint at Intel.　　“I wasn’t going to do something unless it could be bigger than Transmeta — its get big or go home,” said Ditzel in an interview.　　He declined to describe details of his products, their architecture, or even the company’s funding. However, he did give a few examples of his team, which includes Tom Riodan, a former Intel and MIPS processor designer who sold his startup QED to PMC Sierra.　　“He was going to start his own RISC-V company, but we got together instead,” said Ditzel.　　In addition, the startup snagged “a chief architect of the Sony Playstation 3. He was about to start work on the PS5, and when he heard about what we are doing, he said he wanted to join.”　　Advisors include Berkeley professor emeritus David Patterson, who helped launch RISC-V, and Alan Eustace, a veteran senior engineer at Google, HP, and Digital Equipment. Although Ditzel declined to give numbers, the startup has engineers in Silicon Valley and Europe, at least 27 of whom will attend this week’s RISC-V workshop.　　Esperanto’s staff includes former Intel specialists in floating-point and out-of-order design as well as circuit designers and physical layout experts. A compiler team already wrote a shader compiler to run high-end graphics jobs on its chips.　　At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.　　“Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.　　The chips will use 16-bit floating point for training but support lower bit widths and integer operations for neural nets, too. “We will have more performance and fewer watts than competitors and more scalable power — most other [training] chips are hot — we can do lower-power apps as well.”　　Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.　　One of the company’s early targets may be embedded processors for devices such as Amazon Echo or Google Home. Time-to volume was one lesson from his startup Transmeta, said Ditzel, leading to a strategy of “being able to start in broad consumer spaces rather than day-one in servers” where design cycles can span two years.　　The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”　　The relative immaturity of RISC-V and software for it is a chief challenge today.　　“The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”　　“We are in it for the long haul … this is about the next six years, not the next six months.”　　Along the way, Esperanto expects to take a lead role in defining extensions to the RISC-V instruction set. The company employs the co-lead of the foundation’s working group on a vector architecture, and Ditzel led work on extensions to Sun’s Sparc CPU back in the day.　　For its part, Western Digital plans to transition “future core, processor, and controller development” to RISC-V. It currently consumes more than a billion cores a year. It has been a member of the RISC-V Foundation from the outset but has said little about its plans previously.　　“The open-source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal,” said Martin Fink, WD’s CTO in a press statement.　　“For that reason, we are providing all of our RISC-V logic work to the community,” said Fink, who was slated to keynote the event this week. “We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together, we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”　　In an FAQ, the company said that it has no plans to make merchant semiconductors. It positioned the move as an extension of its storage business rather than a replacement of it.
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Release time：2017-11-29 00:00 reading：1106 Continue reading>>
<span style='color:red'>RISC-V</span> Boots Linux at SiFive
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RISC-V Boots Linux at SiFive

　　SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.　　A single 64-bit U54 core delivers 1.7 DMIPS/MHz or 2.75 CoreMark/MHz at 1.5 GHz. It measures 0.234 mm2 including its integrated 32+32KB L1 cache in a TSMC 28HPC process using a 12-track library.　　A quad-core complex with a 2-MByte shared coherent L2 cache, Gbit Ethernet and DDR3/4 controllers and other peripherals measures ~30 mm2. SiFive will deliver a quad-core chip that includes an E51 management core that will ship in the first quarter on boards targeting software developers.　　The single-issue, in-order U54 is expected to lag the performance of ARM’s dual-issue A53. By comparison, in late 2014 Freescale (now NXP) announced the QorIQ LS1043A, a midrange quad-core A53 running at 1.5 GHz delivering more than 16,000 CoreMarks at 6 W.　　SiFive believes its part will be competitive in power and area efficiency. It also aims to innovate in its business model.　　The startup will offer designers 100 prototype SoCs for $100,000 with no fees on third-party IP bundled with its cores until customers ship their chips. “Today, you pay all the IP costs upfront — we think that’s the wrong way,” said Jack Kang, vice president of business development for SiFive.　　It’s still early days for RISC-V vendors and users.　　Microsemi and Arduino are SiFive’s only announced customers. The startup claims that it already has multiple licensees of the U54, including military contractors and large semiconductor companies that serve markets including set-top boxes and data center accelerators.　　Its existing 32- and 64-bit embedded cores have multiple licensees in areas including wearables and storage controllers. Several large chip makers are still evaluating RISC-V for potential use in multiple projects, said Kang.　　For its part, Microsemi uses RISC-V as the PolarFire soft core in its FPGAs. The open source ISA offers lower cost and greater trust given its inspectable RTL, said Bruce Weyer, vice president of Microsemi’s programmable solutions group. He believes those advantages and others will help RISC-V proliferate, but it will take time.　　“We’ve seen rapid adoption of RISC-V in MCUs but there’s a different maturity level in Linux,” Weyer said.　　Processor IP vendors Andes and Cortus announced plans for RISC-V compliant cores earlier this year. The relatively small players are expected to eventually transition to the open-source architecture.　　“It’s hard to put your finger on big market success for RISC-V yet because it’s too early to see SoC and systems shipments,” said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, California).　　“SiFive is certainly making good progress, and with the U54, it can now go after a broader range of embedded designs. The previous products were limited to use with an RTOS or other microcontroller-like designs.”　　As for vendor support, “there’s been a surprising amount of work on RISC-V Linux systems to date using simulators and emulators,” said Kang. “Getting silicon will help spur the software ecosystem.”　　UltraSoC recently joined Rambus as a member of SiFive’s third-party IP program called DesignShare, providing trace and debug tools and SoC monitors. SiFive aims to announce several more IP partners before the end of the year.　　Separately, engineers hope to define a vector version of the RISC-V instruction set by the end of the year, targeting applications such as machine learning. A hypervisor mode is also in the works to enable virtual machines on RISC-V.
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Release time：2017-10-10 00:00 reading：1190 Continue reading>>
Rambus Adds Security to <span style='color:red'>RISC-V</span>
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Rambus Adds Security to RISC-V

　　Startup SiFive announced a new program providing third-party intellectual property blocks for its RISC-V processors. Its first partnership is for security hardware from Rambus.　　Rambus will provide a crypto core optimized to connect to its IoT device management services and run on the SiFive Freedom chips. The Rambus core enables a secure connection, attestation and device monitoring, said Martin Scott, general manager of Rambus’s security group.　　The core is the first member of what SiFive calls DesignShare. “SiFive welcomes everybody to join DesignShare — Rambus is the first of many partners we will be announcing soon,” said Jack Kang, vice president of product and business development at the startup.　　The program aims to deliver IP “at a low or reduced up front cost,” he said. The blocks will not necessarily be based on open source code.　　SiFive officially launched in May its first two cores available on its Web site. Although the RISC-V instruction set is open source, the cores require a one-time licensing fee. SiFive does not charge per-unit royalties.　　SiFive CTO and co-founder Yunsup Lee will give a talk at Hot Chips this week about the company’s products first announced in 2016 as well as the Rambus partnership.　　Earlier this month, SiFive named industry veteran Naveed Sherwani its CEO. Sherwani has helped found nine startups to date including Open Silicon and Brite Semiconductor. He also helped pioneer Intel’s move to a more open EDA platform for its first ASIC service.
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Release time：2017-08-22 00:00 reading：1206 Continue reading>>
<span style='color:red'>RISC-V</span> Cores Get Support, Fees
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RISC-V Cores Get Support, Fees

Instruction sets may want to be free, but cores--maybe not so much. Startup SiFive announced a new embedded RISC-V core and a relatively simple way to access its processor cores on its Web site, however, they come with one-time licensing costs in the mid-six figures. SiFive made its existing 32-bit E31 core and a new 64-bit E51 version available for one-time fees of about $300,000 and $600,000, respectively. An open source core called Rocket created by some of SiFive's founders remains available for free online. It can be used to configure and generate 32- and 64-bit processor cores. The SiFive news comes just before the sixth workshop of the RISC-V open instruction set group, its first in China. SiFive will have to compete with a wide range of cores from Cadence, Cortus, Imagination, Synopsys and Andes--which rolls out its first 64-but core next week. The existing players have more mature ecosystems and cores that also sell for less than a million dollars, said Linley Gwennap, principal of the Linley Group (Mountain View, Calif.). “I thought their original business model was the core would be open source, so they seem to have changed their business model…They are trying to innovate but at the end of the day everyone has costs,” Gwennap said. “A year ago there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive. SiFive provides just the processor core, but researchers at Berkeley and elsewhere have released other elements such as the TileLink interface. (Image: SiFive) The E31 and E51 come with a warranty the cores will hit a specified performance target as well as indemnification, documentation, test benches, constraint files and integration files. “The analogy here is with Red Hat that provides a package with support,” said Kang. SiFive points to the value of making its silicon IP easy to access and royalty-free. Royalties are not a big issue for engineers who typically forecast their lifetime needs for a core and figure that into a total negotiated price," said Gwennap. Datasheets and other detailed information to evaluate the cores, including FPGA bitstream models and an evaluation version of functional, synthesizable RTL for the E31 are freely available on the company’s Web site. The site also lets engineers configure cores and buy them after agreeing to a seven-page licensing contract online. “The ability to try, configure and buy a core over the Web is unheard of, and there’s no royalties so you don’t have to figure out how many you are going to sell,” said Kang. “You can buy all sorts of software online and can even set up an Amazon data center service with a few clicks, so why is the silicon IP industry so far behind?” asked Kang. “We have to get IP from others and it’s incredible how hard it is, so we have a chance to do something new for the industry,” he said. Both the E31 and E51 can run at data rates up to 1.4 GHz in a 28 nm process. The E31 is roughly comparable to an ARM Cortex M3 or M4. The E51 creates a new entry-level for an embedded 64-bit core below ARM’s Cortex A53. Neither core runs Linux, SiFive plans to roll out a separate U54 core for standalone processors running Linux later this year. It may roll out an additional E-series cores before the end of the year. FreeRTOS, Project Zephyr and Apache Minute OSes have been ported to the current E31 core. The RISC-V architecture now has available a GCC compiler for C, a GNU debugger and other peripheral tools. SiFive provides an SDK and an Eclipse-based development environment. “There’s been huge progress in the RISC-V ecosystem,” said Kang.
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Release time：2017-05-05 00:00 reading：1199 Continue reading>>

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