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Samsung Starts Shipping Industry-First <span style='color:red'>HBM</span>4E Samples 3 Months After <span style='color:red'>HBM</span>4 Ramp; Performance Up 20%+

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Samsung Starts Shipping Industry-First HBM4E Samples 3 Months After HBM4 Ramp; Performance Up 20%+

　　Just months after rolling out HBM4 shipments in early 2026, Samsung has begun providing samples of the industry’s first 12-layer HBM4E to major global partners, according to the company’s latest press release.　　Given that HBM4 shares the same 1c DRAM process and 4nm base die architecture as HBM4E, and is already in mass production, industry observers suggest the newly shipped HBM4E samples are also well positioned to transition into mass production. Samsung adds that it plans to proceed with HBM4E mass production in line with client-specific timelines.　　Meanwhile, Samsung is also expanding mass production and supply of HBM4, which became the world’s first HBM4 to enter mass production and shipment in February. In December last year, Samsung’s HBM4 received top-tier evaluation after demonstrating an industry-leading 11.7Gbps speed in System-in-Package (SiP) testing, the final certification stage, the company adds.　　According to News1, the latest development makes Samsung the first to supply HBM4E. Industry observers cited by the report also noted that starting from HBM4, customer-specific design flexibility and stable large-scale supply capabilities will become even more critical. Against this backdrop, Samsung’s integrated strengths across memory, foundry, and advanced packaging are expected to stand out even more clearly, the report adds.　　HBM4E Upgrade with 20% Performance Boost, 30% Higher Capacity　　In terms of performance, Samsung notes that HBM4E marks a notable upgrade over the previous generation, offering a stable 14Gbps pin speed that can scale up to 16Gbps for more demanding AI workloads. Compared with HBM4, the new memory delivers over 20% higher performance and reaches bandwidth of up to 3.6TB/s per stack, significantly improving compute efficiency for large language models (LLMs) and next-generation AI systems.　　Additionally, Samsung’s 12-layer HBM4E is currently offered in a 48GB capacity, which is more than 30% higher than the previous generation. The company plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) variants to better align with diverse customer requirements as well.　　From an efficiency standpoint, Samsung highlights that advanced low-power design techniques and an optimized packaging architecture have improved energy efficiency by 16% while reducing thermal resistance by more than 14% compared with the previous generation.　　HBM4E Progress Among Rivals　　Meanwhile, progress from SK hynix and Micron in HBM4E has come under closer market scrutiny following Samsung’s advances. According to Yonhap News Agency, SK hynix had initially planned to begin HBM4E sample shipments in the second half of this year, but recent reports indicate smoother-than-expected development progress, bringing forward its timeline.　　On the other hand, Micron said its first HBM4E product will follow JEDEC standards, with mass production ramp-up targeted for 2027, according to STOCK Analysis.

Key word：

Samsung

Release time：2026-05-29 10:18 reading：352 Continue reading>>

SK hynix Introduces i<span style='color:red'>HBM</span> Solution, Targets <span style='color:red'>HBM</span>5 Adoption with 30% Thermal Resistance Reduction

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SK hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction

　　As thermal management emerges as a key challenge for HBM, SK hynix has unveiled its iHBM solution, which integrates cooling elements (ICEs) directly into the HBM package. The company plans to adopt the technology in next-generation products, including HBM5, according to its press release.　　According to SK hynix, unlike conventional HBM designs that dissipate heat through the core die, iHBM integrates cooling elements (ICEs), made of thermally conductive, electrically non-conductive silicon-based materials, directly into the D2D PHY between HBM and GPUs, where heat is most concentrated. The company said the technology reduces thermal resistance by 30% and improves operating stability.　　As highlighted by SK hynix, the iHBM solution adopts a structural approach to thermal management by creating an additional heat dissipation path within the package. It also leverages the company’s wafer-level packaging (WLP) process and proven MR-MUF technology to enable stable high-volume manufacturing.　　In addition, its compatibility with existing System-in-Package (SiP) architectures allows customers to adopt the thermal solution with minimal design modifications, SK hynix adds.　　In terms of future roadmap, SK hynix plans to incorporate the iHBM solution into next-generation HBM products, including HBM5, with the goal of improving the stability and efficiency of HPC systems and AI data centers.　　Another Key Technology beyond Hybrid Bonding　　Alongside SK hynix’s latest iHBM solution, hybrid bonding is widely seen as a key approach to addressing heat dissipation challenges in 20-stack HBM, which, as previously reported by The Elec, are expected to become increasingly difficult.　　As explained in the report, hybrid bonding differs from conventional thermo-compression (TC) bonding, which connects chips through soldered micro-bumps. Instead, it bonds dielectric materials such as silicon dioxide (SiO₂) and copper through an annealing process at temperatures of roughly 200°C to 400°C.　　By heating and gradually cooling copper sealed within dielectric layers, thermal expansion and vertical pressure enable direct copper-to-copper diffusion bonding without reaching copper’s melting point, the report notes, adding this approach helps reduce thermal damage to semiconductor circuits while delivering improved thermal and electrical performance.

Key word：

SK hynix

Release time：2026-05-27 10:42 reading：384 Continue reading>>

Micron More Upbeat on Outlook, Reportedly Sets 2027 <span style='color:red'>HBM</span>4E Ramp with TSMC for Standard, Custom Logic Dies

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Micron More Upbeat on Outlook, Reportedly Sets 2027 HBM4E Ramp with TSMC for Standard, Custom Logic Dies

　　Two months after its March earnings call, Micron is turning more upbeat on its outlook, while providing additional details on its custom HBM development progress. At the J.P. Morgan 54th Annual Global Technology, Media and Communications Conference, Micron’s Global Operations EVP Manish Bhatia, via STOCK Analysis transcript, said the company’s first HBM4E will be a JEDEC-standard product, with ramp-up scheduled for 2027.　　While Micron is still using 1-beta DRAM for HBM4, Bhatia said the company is expected to transition to 1-gamma DRAM in the HBM4E era. He also confirmed that the logic dies for both standard and custom HBM4E are expected to be manufactured by TSMC.　　When asked about the margin profile of customized products, Bhatia, according to STOCK Analysis, highlighted that value creation stems from multiple proprietary layers: design innovation, robust core DRAM development, and advanced packaging.　　He emphasized that customization represents the next evolution of this value expansion, and as the value increases, customers are expected to be willing to pay for the added customization.　　Improving Outlook vs. Previous Earnings Call　　According to Bhatia, Micron now expects tight conditions across HBM, DRAM, and NAND to persist well beyond 2026. Thus, he noted that the financial outlook has strengthened since the company’s last earnings call, and it is on track for another substantial record free cash flow in fiscal Q3.　　Notably, Bhatia pointed out that while pricing has largely played out as expected, demand remains very strong. He added that the AI ecosystem is shifting from human interactions to agentic and even machine-to-machine workflows, with these agentic workloads increasingly driving inference demand. As inference takes up a larger share of workloads, memory is increasingly seen as a strategic asset for customers, he said.　　Against this backdrop, Micron said in March that it had secured its first strategic customer agreement—a five-year deal with a large customer. Since then, the company has made meaningful progress on additional SCAs, with other customers also showing strong interest in establishing similar strategic relationships with Micron, including in NAND, Bhatia said.　　India Capacity Reported Booked up　　Amid tight demand, Bhatia also said Micron’s global expansion is accelerating. He noted that its Idaho 1 site is progressing well, with the company pulling forward its wafer output timeline from the second half of 2027 to mid-2027.　　Surging memory demand is also driving ramp-up at Micron’s new semiconductor assembly and test facility in Sanand, Gujarat, which began operations in late February. In a separate report by Business Standard, Micron’s entire memory production capacity in India has been fully booked amid strong demand.　　According to a previous Business Standard report, at full capacity, the facility could account for up to 10% of Micron’s global output, supplying both domestic and international markets.　　Sumit Sadana, executive vice-president and chief business officer at Micron, reportedly told Indian media outlet The Economic Times that the global semiconductor memory shortage triggered by the AI boom is proving far more severe than many companies currently anticipate, with the crunch potentially extending well beyond 2028 despite aggressive capacity expansion across the industry.

Key word：

Micron

Release time：2026-05-25 10:44 reading：422 Continue reading>>

NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond <span style='color:red'>HBM</span>

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NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond HBM

　　As AI models continue to scale, HBM may struggle to meet future memory-capacity demands, prompting industry experts to view GPU-driven storage architectures as a potential next frontier. According to The Elec, NVIDIA and Amazon are reportedly advancing storage architectures that allow GPUs to directly control storage devices such as SSDs. NVIDIA is said to plan the introduction of GPU-Initiated Direct Storage Access (GIDS) starting with its Vera Rubin AI platform, a shift that could accelerate the emergence of high-bandwidth flash (HBF), the report notes.　　Citing Song Ki-hwan, a professor in the Department of System Semiconductor Engineering at Yonsei University, the report explains that GIDS goes beyond existing GPU Direct Storage (GDS) architecture. Under GDS, CPUs issue data requests to storage devices before data is transferred to GPUs. GIDS advances this by allowing GPUs to access storage directly, bypassing CPUs and DRAM.　　Both GIDS and GDS aim to overcome data-transfer bottlenecks tied to traditional von Neumann computing architectures. Microsoft and AMD are also said to be exploring similar approaches. The report, citing Song, adds that traditional data-transfer methods are inefficient because CPUs are structurally limited in thread processing, while GPUs can generate tens of thousands of parallel threads. Song also notes that GPU-HBM data transfer already accounts for roughly half of total system power, strengthening the case for HBF architectures that place ultra-fast NAND closer to GPUs to address future AI bottlenecks.　　GIDS Could Accelerate HBF and Expand NAND’s Role in AI Memory　　The emergence of GIDS could allow NAND storage to take on a larger role in AI memory systems while easing pressure on HBM capacity. As the report notes, this shift would require higher-performance NAND flash capable of keeping pace with GPU processing speeds. One proposed approach is high-bandwidth flash (HBF), which stacks NAND flash vertically in a structure similar to HBM and connects it using through-silicon vias (TSVs).　　The report notes that NAND flash offers roughly 30 times higher bit density than DRAM, enabling far greater memory capacity in a similar footprint. According to Song, combining six HBF units with two HBM units could increase GPU memory capacity more than 16 times, from 192GB to 3,120GB, potentially supporting AI models with parameter sizes around 16 times larger than current architectures.　　Still, NAND flash has endurance limits, typically supporting only around 100,000 write-and-erase cycles versus DRAM’s near-unlimited write capability. As a result, HBF is seen as better suited for storing AI model parameters, which remain largely unchanged during inference and function as read-only workloads.　　Meanwhile, memory makers have also been exploring GPU-driven memory architectures. According to an Edaily report last year, sources said Samsung Electronics is actively researching next-generation high-performance Z-NAND. The company is also developing GIDS technology that would allow GPUs to directly access Z-NAND-based storage devices. If implemented, GPUs would be able to access Z-NAND devices without intermediaries, potentially shortening processing times for AI workloads.

Key word：

NVIDIA

Release time：2026-05-20 11:20 reading：814 Continue reading>>

Samsung Reportedly Develops Mobile <span style='color:red'>HBM</span> Packaging With Copper Pillars, Bandwidth Up 15%–30%

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Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%

　　Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.　　The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.　　More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.　　The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.　　Commercialization Timeline Remains Unclear　　Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.　　Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.　　SK hynix Advances Mobile AI Packaging　　SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.　　Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.

Key word：

Samsung

Release time：2026-05-15 10:49 reading：697 Continue reading>>

AI Fuels Next-Gen <span style='color:red'>HBM</span> Demand

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AI Fuels Next-Gen HBM Demand

　　High bandwidth memory gained some momentum last week as Samsung Electronics announced it started mass production of its second-generation technology, dubbed Aquabolt.　　Designed for use with next-gen supercomputers, artificial intelligence (AI) and graphics systems, Tien Shiah, product marketing manager for High Bandwidth Memory at Samsung, said the 8 GB High Bandwidth Memory-2 (HBM2) offers the highest DRAM performance levels and the fastest data transmission rates available today with a 2.4 gigabits-per-second (Gbps) data transfer speed per pin at 1.2V. That's nearly a 50 percent performance improvement per package, he said, compared with Samsung's previous generation HBM2 package, Flarebolt, with its 1.6Gbps pin speed at 1.2V and 2.0Gbps at 1.35V.　　In a telephone interview with EE Times from CES, Shiah said a single Aquabolt package will offer a 307GBps data bandwidth, achieving 9.6 times faster data transmission than an 8Gb GDDR5 chip, which provides a 32GBps data bandwidth. This means using four packages in a system will enable a 1.2 terabytes-per-second (TBps) bandwidth, he said, hence the overall system performance by as much as 50 percent.　　A need for even faster access to data is driving adoption of HBM, said Shiah, particularly AI and machine learning algorithms. He added that HBM is the fastest form of DRAM on the market and offers both space and power savings. "You have it all in a single package,” he said.　　However, Shiah said, this configuration requires expertise in design as HBM has to be integrated in the ASIC with silicon interposers.　　Samsung also made use of its expertise in through-silicon via (TSV) technology related to thermal control, said Shiah. A single Aquabolt package consists of eight 8Gb HBM2 dies, which are vertically interconnected using more than 5,000 TSVs. Samsung also increased the number of thermal bumps between the HBM2 dies, which enables stronger thermal control in each package. Finally, there's protective layer at the bottom, which increases the package's overall physical strength.　　HBM is often discussed in the same breadth of Hybrid Memory Cube (HMC) as an avenue for getting the fastest DRAM performance. There's not a great deal of difference between the two technologies, but given that HBM has been getting wider adoption, it may win out over HMC, just as VHS eclipsed Beta.　　But even if HBM is the winner, it's still a niche technology, said Jim Handy, principal analyst with Objective Analysis. "I do see it eventually becoming mainstream, but today it's really expensive technology. That's because TSVs are expensive thing to put silicon wafers,” Handy said.　　HBM has been somewhat stealthy to date, normally used in Nvidia and AMD graphics cards, where a whole lot bandwidth needs to get to the GPU, he said.　　While TSVs do offer advantages over wire bonding, especially when your can put 5,000 TSVs on a chip, it's still relatively expensive, Handy said. "There's a hump to get over with any technology like this," Handy said. "The price will go down as volume goes up, but high prices keep volume down.”　　That's why it's still mainly found in high-end GPU cards, Handy said, and moving into some supercomputers now, and will be in standard servers at some point.　　"It's hard to tell what's going to drive high enough volumes to get the costs down,” Handy added. "Everybody argues about how AI is going to fit into picture.”　　There's a big push toward FPGAs for AI that provide competition for GPUs. Handy said smartphones could be target markets for HBM in the long run given that GDDR5 is finding its way into those devices.　　As for the HBM vs. HMC debate, the difference is the logic chip at the bottom, said Handy, and although Intel went with Micron's HMC technology, it developed its own logic standard. And like Samsung, the remaining DRAM maker, SK Hynix, has gone the HBM route. He could see Intel moving from its HMC variant over to HBM, and ultimately, Micron.　　"There's not much difference between HBM and HMC," Handy said. "There's not a lot lost by Micron if it has to convert.”

Key word：

AI,HBM

Release time：2018-01-17 00:00 reading：1529 Continue reading>>

model	brand	Quote
BD71847AMWV-E2	ROHM Semiconductor
RB751G-40T2R	ROHM Semiconductor
MC33074DR2G	onsemi
TL431ACLPR	Texas Instruments
CDZVT2R20B	ROHM Semiconductor

model	brand	To snap up
BU33JA2MNVX-CTL	ROHM Semiconductor
BP3621	ROHM Semiconductor
IPZ40N04S5L4R8ATMA1	Infineon Technologies
ESR03EZPJ151	ROHM Semiconductor
STM32F429IGT6	STMicroelectronics
TPS63050YFFR	Texas Instruments

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