Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%

　　Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.

　　The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.

　　More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.

　　The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.

　　Commercialization Timeline Remains Unclear

　　Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.

　　Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.

　　SK hynix Advances Mobile AI Packaging

　　SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.

　　Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.