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Chinese Firm to Buy NXP <span style='color:red'>Spin</span>off
NYU <span style='color:red'>Spin</span>off Develops 5G Emulator
  5G consists of a host of technologies that include mmWave frequencies and multiple antennas. Because mmWave signals must overcome losses not encountered at lower frequencies, the industry is moving to multiple antennas and phased-array technology that direct signals to their destination with higher power than today's omnidirectional signals. Testing such systems is difficult, but a startup out of NYU Tandon School of Engineering may just make channel emulation practical and affordable.  Started by post-doctoral research fellow Aditya Dhananjay and NYU faculty members Sundeep Rangan and Dennis Shasha, Millilabs has developed a system that uses off-the-shelf hardware that emulates both the transmission channel and the phased-array antennas needed to produce MIMO signals.  Because 3G and 4G signals are omnidirectional and operate at frequencies below 6 GHz, signal power is strong enough to overcome many transmission losses. Not so with mmWave signals starting at 24 GHz. EE Times spoke with Aditya Dhananjay about Millilabs and its technology.  Using PXI instruments, the Millilabs emulator (Figure 1) incorporates National Instruments FPGA cards that emulate the conditions that signals might encounter in a live situation. The system uses analog-to-digital converter (ADC) cards to emulate signals sent from an antenna. After signal processing is done with two FPGA cards, the digital signals go to digital-to-analog converters (DACs), which emulate signals from the receiving antennas.  According to Dhananjay, the FPGAs can adjust the following conditions:  Noise figure  Number of antenna elements. While the current system emulates up to 1,024 antennas, there is theoretically no limit.  Spacing of antenna elements, such as λ/4 and λ/2  Polarization (horizontal, vertical, and circular)  Errors in phased arrays  Beamforming vector and noise imperfections  Phase noise  System clocks (CMOS and crystal sources)  Dhananjay explained why this development is significant: "With traditional emulation, the cost of building an emulator scales linearly with the number of antenna elements. For example, emulating a 64-antenna system will need 64 times the amount of hardware than a single-antenna system. The MilliLabs Emulator supports beamforming with hundreds of antenna elements, which is our key technology."  By emulating antennas and the transmission channel, the Millilabs system eliminates the need for antenna arrays and their associated wires. Designers need only provide the analog or digital signals from a transmitter and provide a receiver (Figure 2).  "By virtue of the joint channel and front-end emulation, the hardware cost doesn't change as you increase the number of antennas," said Dhananjay. "The relative cost savings depends on the number of antennas compared to traditional systems."
Release time:2018-01-30 00:00 reading:1197 Continue reading>>
Everspin Targets Niches for MRAM
  Consistent challenge with emerging memories: the volume must go up for the price to come down, and the price has to come down for the volume to go up. Everspin Technologies is hoping, however, that specific industries will favor value over price-per-bit as it ramps up production of its MRAM.  The MRAM pioneer just released an application white paper for its nvNITRO solution being jointly delivered with SMART Modular Technologies. The two companies collaborated on the development of the nvNITRO NVMe storage accelerator and are focusing on jointly developing several vertical markets, the first being the financial technology (FinTech) sector, where nvNITRO can increase data throughput and reduce critical storage bottlenecks, according to Pat Patla, senior vice president of marketing at Everspin.  In a telephone interview with EE Times, Patla said the nvNITRO NVMe storage accelerator enables a 90 percent reduction in latency for financial transactions, which helps fintech companies meet compliance rules that often need synchronous logging. This adds latency and creates transaction processing bottlenecks. As outlined in the whitepaper, nvNITRO's ability to reduce latency so significantly enables fintech companies to log transactions faster so they can increase their overall transaction volume, and ultimately, their revenue. Meanwhile, the persistence of STT-MRAM also contributes to necessary compliance as all data logs are protected.  The vertical focus comes as Everspin has started mass-production of its STT-MRAM. The company hit a notable milestone of recording revenue for its first 40nm 256Mb STT-MRAM products in the fourth quarter of 2017 and is ramping its volume production in 2018. There are handful of companies working an MRAM, but Everspin is the only company that's commercially delivering both discrete and embedded MRAM products, thanks in part to its collaboration with GlobalFoundries.  Everspin is touting its 256Mb STT-MRAM as the first ever perpendicular MTJ STT-MRAM entering mass production. Patla said its ST-DDR3 / ST-DDR4 interface was designed to be as close to standards as possible so that customers can easily integrate it into their systems with a couple of tiny changes, primarily to the memory controller. Everspin's STT-MRAM is also NVMe-compliant.  Patla acknowledges that until there's a standard in place, there will be concerns from customers about sole-sourcing the technology. “DDDR5 is where everyone is convening," he said.  The company is focusing on areas where there is a need for fast, persistent memory by offering near-DRAM performance combined with non-volatility. “Flash offers great performance next to rotating media, but against DRAM or MRAM, it significantly slower," Patla said. He describes spin torque MRAM as a three-legged stool comprised of performance, endurance and bit air rate, with non-volatility has the seat.  Aside from specific industry verticals such as fintech that see value in adopting MRAM, Patla said Everspin is targeting three buckets: artificial intelligence (AI), edge computing and digital transformation, which includes data center applications. Because MRAM only users power when reading and writing, it's ideal for edge computing environments as demand for processing outside the data center increases and Internet of Things deployments grow.  Price is not the key driver of MRAM adoption, said Patla. Instead, specific applications that need fast, persistent memories are guiding customers' decisions. “People are buying based on the value proposition rather than dollars per gigabyte," he said.  Right now, the price of MRAM is still rather high, said Thomas Coughlin, founder of Coughlin Associates, but it is the most interesting emerging memory technology because its performance is close to SRAM and DRAM, and its endurance is very high. Coughlin said MRAM makes sense for cache buffering, and for specific applications, such as the nvNITRO NVMe storage accelerator for financial applications.  “Doing a transaction quickly is important, but having a record is just as important," Coughlin said. "It's an interesting case study. Time is money, and they're making more money than they're spending."  Coughlin said specialized niche markets are willing to pay for the combination of speed and non-volatility of MRAM. He noted that Everspin has already shipped more than 70 million units, and its partnership with GlobalFoundries for wafers and embedded products opens up possibilities for increased volume. Satisfying niche markets that pulls in more volume will help Everspin's MRAM become more mainstream. “That's where GlobalFoundries' products come in," he said.  The interesting possibilities for MRAM are bolstered by the fact that Samsung and TSMC will be producing MRAM products this year, too, said Coughlin. “That leads me to the think there's a general perception MRAM has a place," he said.  As other MRAM makers mature, such as Spin Transfer Technologies, competition could lead to a squeeze on prices. Having more than one supplier creates a more vibrant market, Coughlin said, and 2018 will be an important year in terms developing a viable supply chain.  MRAM is not going replace SRAM and DRAM right in any applications right away, Coughlin, but there is a gap between those memories and NAND flash to filled. “3D Xpoint is trying to fill this gap, but is still far away from DRAM," he said. It's also important to remember that flash took decades to become competitive with hard drives, he added.  In the meantime, ReRAM and FRAM are both worth watching as emerging memories to fill the gap between DRAM and flash, said Coughlin. “It's a veritable zoo of technologies and we'll have to wait and see which animals survive the evolutionary process," he added.
Release time:2018-01-23 00:00 reading:2827 Continue reading>>
Two spin-off founders to industrialise adhesive health-monitoring electrode
  An elastic electrode has been developed by ETH Zurich researchers as an alternative to the generic designs. The researchers aim to create an electrode that is comfortable, suitable for taking measurements over longer periods and minimise the risk of skin irritation.  The material is made of what the researchers describe as a non-irritant mixture of silicone rubber and conductive silver particles.  The mechanism that allow grasshoppers to walk even on vertical surfaces was inspiration for the device’s surface structure, which enables the electrode surface to adhere to the skin. The idea behind this is that users will barely notice it, while signals from the heart to the brain should record in higher quality due to maximised contact surface between skin and electrode.  Two of the study’s authors, Séverine Chardonnens and Simon Bachmann, want to turn this into a marketable product as early as this year.  were keen to see the idea to market and after staring their own company, were accepted on to the Venture Kick and CTI funding programmes.  The duo are said to have made a good deal of seed capital through start-up competitions.  Having developed a prototype electrode and the official founding of IDUN Technologies as an ETH spin-off in November 2017, Chardonnens and Bachmann are considering which application to focus upon.  Bachmann said: “Commercialisation is worthwhile in applications where the new electrodes offer the biggest advantages over existing models. We see potential in the long-term monitoring of patients, in sports performance monitoring and in the EEG market.”  Once strategic orientation has been settled, the focus will turn to industrialisation and the acquisition of partners and customers.  Chardonn added: “If everything goes as planned, we will be able to sell the first electrodes as early as this year.”
Release time:2018-01-17 00:00 reading:1226 Continue reading>>
RISC-V <span style='color:red'>Spin</span>s into Drives, AI
  Storage giant Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture. The two moves suggest that RISC-V has emerged as a viable — but not yet mature — alternative to ARM and the x86.  Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.  For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.A 16-core “ET-Maxion” targeting highest single-thread performanceA 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.  “Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem, and having a startup try to take it to high-end products is a big deal because to date, RISC-V has been mainly in low-end microcontrollers for the IoT,” said Linley Gwennap, principal of market watcher The Linley Group.  Esperanto has kept a tight lid on its plans to date, although its chief executive, microprocessor veteran David Ditzel, has been a fixture at RISC-V events for some time. Ditzel designed server processors at the former Sun Microsystems and startup Transmeta before doing a relatively short stint at Intel.  “I wasn’t going to do something unless it could be bigger than Transmeta — its get big or go home,” said Ditzel in an interview.  He declined to describe details of his products, their architecture, or even the company’s funding. However, he did give a few examples of his team, which includes Tom Riodan, a former Intel and MIPS processor designer who sold his startup QED to PMC Sierra.  “He was going to start his own RISC-V company, but we got together instead,” said Ditzel.  In addition, the startup snagged “a chief architect of the Sony Playstation 3. He was about to start work on the PS5, and when he heard about what we are doing, he said he wanted to join.”  Advisors include Berkeley professor emeritus David Patterson, who helped launch RISC-V, and Alan Eustace, a veteran senior engineer at Google, HP, and Digital Equipment. Although Ditzel declined to give numbers, the startup has engineers in Silicon Valley and Europe, at least 27 of whom will attend this week’s RISC-V workshop.  Esperanto’s staff includes former Intel specialists in floating-point and out-of-order design as well as circuit designers and physical layout experts. A compiler team already wrote a shader compiler to run high-end graphics jobs on its chips.  At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.  “Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.  The chips will use 16-bit floating point for training but support lower bit widths and integer operations for neural nets, too. “We will have more performance and fewer watts than competitors and more scalable power — most other [training] chips are hot — we can do lower-power apps as well.”  Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.  One of the company’s early targets may be embedded processors for devices such as Amazon Echo or Google Home. Time-to volume was one lesson from his startup Transmeta, said Ditzel, leading to a strategy of “being able to start in broad consumer spaces rather than day-one in servers” where design cycles can span two years.  The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”  The relative immaturity of RISC-V and software for it is a chief challenge today.  “The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”  “We are in it for the long haul … this is about the next six years, not the next six months.”  Along the way, Esperanto expects to take a lead role in defining extensions to the RISC-V instruction set. The company employs the co-lead of the foundation’s working group on a vector architecture, and Ditzel led work on extensions to Sun’s Sparc CPU back in the day.  For its part, Western Digital plans to transition “future core, processor, and controller development” to RISC-V. It currently consumes more than a billion cores a year. It has been a member of the RISC-V Foundation from the outset but has said little about its plans previously.  “The open-source movement has demonstrated to the world that innovation is maximized with a large community working toward a common goal,” said Martin Fink, WD’s CTO in a press statement.  “For that reason, we are providing all of our RISC-V logic work to the community,” said Fink, who was slated to keynote the event this week. “We also encourage open collaboration among all industry participants, including our customers and partners, to help amplify and accelerate our efforts. Together, we can drive data-focused innovation and ensure that RISC-V becomes the next Linux success story.”  In an FAQ, the company said that it has no plans to make merchant semiconductors. It positioned the move as an extension of its storage business rather than a replacement of it.
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Release time:2017-11-29 00:00 reading:1106 Continue reading>>
<span style='color:red'>Spin</span> current from heat: new material increases efficiency
  Physicists at Bielefeld University have found a way to use the heat from electronic devices to create energy, applying the heat to generate magnetic signals known as ‘spin currents’.  According to researchers it could be possible in the future to use these signals to replace some of the electrical current currently used in electronic components.  In a new study, physicists from the University of Greifswald, Gie?en University, and the Leibniz Institute for Solid State and Materials Research in Dresden tested which materials generated this spin current most effectively from heat. Their findings have been published in the research journal ‘Nature Communications’.  The Bielefeld physicists are working on the basic principles for making data processing more effective and energy-efficient in the young field of ‘spin caloritronics’ and the study determines the strength of the spin current for various combinations of thin films.  A spin current is produced by differences in temperature between two ends of an electronic component. These components are extremely small and only one millionth of a millimetre thick. Because they are composed of magnetic materials such as iron, cobalt, or nickel, they are called magnetic nanostructures.  The physicists take two such nanofilms and place a layer of metal oxide between them usually only a few atoms thick. One of the external films is then heated and then electrons with a specific spin orientation then pass through the metal oxide. This produces the spin current.  The teams led by Dr. Alexander B?hnke and Dr. Torsten Hübner have tested different combinations of ultra-thin films. ‘Depending on which material we used, the strength of the spin current varied markedly,’ says B?hnke. ‘That is because of the electronic structure of the materials we used.’  According to the researchers, magnetic nanostructures with special combinations made up of cobalt, iron, silicon, and aluminium were particularly productive.  The study is one of a number of projects in the ‘Spin Caloric Transport’ (SpinCaT) Priority Programme of the German Research Foundation (DFG).
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Release time:2017-11-21 00:00 reading:1086 Continue reading>>
<span style='color:red'>Spin</span> Transfer, TEL Partner on MRAM Process Development
  MRAM developer Spin Transfer Technologies (STT) and capital equipment vendor Tokyo Electron Ltd. (TEL) have entered into a collaborative engineering program to jointly develop process technologies for SRAM- and DRAM-class spin-transfer torque (ST) MRAM devices.  The project will combine TEL's ST-MRAM deposition tool and knowledge of the formation capabilities of magnetic tools with STT's high-endurance perpendicular magnetic tunnel junction (pMTJ) design and device fabrication technology, the companies said. The goal of the project is to further advance ST-MRAM to provide previously unachievable levels of speed, density and endurance, they said.  MRAM (magnetoresistive random access memory) has long been seen as a potential replacement for SRAM, DRAM and flash, but development, which began in earnest in the 1990s, has been slow. To date, only one company, Everspin Technologies, has shipped working MRAM products. Everspin has been shipping MRAM since 2006, when it was part of Freescale Semiconductor, and claims to have shipped more than 60 million MRAM devices.  Embedded SRAM — pervasive in mobile, computing and industrial applications — is considered a fast and high endurance memory, but is also costly, power hungry and volatile. ST-MRAM, which is more compact, is considered less costly, nonvolatile and requires less power when storing data. But further improvements — especially in terms of fast switching and endurance — are needed for ST-MRAM to match or exceed SRAM performance.  Last August, Everspin became the first vendor to announce it was sampling MRAM with pMTJs — considered by all vendors developing MRAM to be the technology offer the best scalability, shape dependence and magnetic scalability. In January of this year, STT also began sampling pMTJs.  STT and TEL said the collaborative agreement would further each company's goal of offering compelling MRAM solutions for the embedded SRAM market initially and, eventually, the standalone DRAM market. The companies aim to develop MRAM is pMTJs smaller than 30nm, more dense than today's commercially available products.  Tom Sparkman, who took over as CEO of STT in July, said in a press statement that the partnership with TEL would speed the development of the company's technology for replacing SRAM and DRAM.  "We believe the adoption of ST-MRAM will materially exceed current expectations, and we are excited to work with TEL to revolutionize the ST-MRAM market by achieving the speed, density and endurance the industry needs,"
Release time:2017-10-17 00:00 reading:2282 Continue reading>>
MIT <span style='color:red'>Spin</span>s Second Wireless Charger Start-up
  The Massachusetts Institute of Technology has spun off a second wireless recharging start-up. Pi Inc. (San Bruno, Calif.), which made its formal debut this week, is readying a beam-forming magnetic induction wireless recharging station that will charge multiple devices within a range of about a foot from the charger in any direction.  Pi’s rollout comes roughly a decade after MIT spin-off WiTricity Corp. (Watertown, Mass.) first promised a magnetically coupled resonant wireless recharger that would work over a distance of up to 3 feet. Neither technology has appeared in a product yet, although both spin-offs are promising announcements by Christmas.  There are already more than 700 wireless rechargeable devices and chargers available that adhere to the Wireless Power Consortium’s licensable Qi standard, which works over a distance of about an inch. All of these chargers and wirelessly rechargeable devices — such as Apple’s new iPhone-8 — use a pad on which the user places the device for wireless charging via resonant inductive coupling. There are also 14 Qi-compatible chargers designed to be built into furniture for a planar profile.  Pi says its solution is also Qi-compatible but will extend the charging reach from 1 inch to 12 inches for roughly a $200 price tag (compared with $80 for Apple’s pad and as little as $35 for a Chinese knockoff).  Other start-ups, such as Energous Corp. (San Jose, Calif.) and Ossia Inc. (Bellevue, Wash.), are promising resonant rechargers with up to a 30-foot range, albeit at a higher cost than for solutions conforming to the Qi standard. Those companies have yet to deliver products, however.  The open question is whether consumers will be willing to install a beaming device of any kind — especially at a price of $200 — simply to extend the range of a wireless charger, particularly as furniture pieces with built-in, zero-profile chargers become increasingly available. Investors have been bullish on the concept, however. Intel Capital and Foxconn invested $25 million in WiTricity a few years ago to ensure that company’s success, which might soon be in the offing. Only time will tell.
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Release time:2017-09-26 00:00 reading:1304 Continue reading>>
Everspin Appoints New CEO
  Magnetoresistive random access memory (MRAM) supplier Everspin Technologies Inc. announced it is replacing its CEO with longtime SanDisk executive Kevin Conley.  Everspin, the leading supplier of MRAM, said Conley will take the reins on Sept. 1, replacing Phill LoPresti. LoPresti, who has been CEO of Everspin since 2010, who step down as CEO Aug. 31 but remain as an advisor to the company for six months, Everspin (Chandler, Ariz.) said.  Conley joined Everspin's board of directors in March. He spent 15 years at SanDisk, including a stint as chief technology and another as vice president and general manager of the firm's Client Storage Solutions business. He also previously served as vice president of engineering for Corsair Components Inc. He is listed as the inventor or co-inventor on more than 80 patents in the area of non-volatile memory architecture and management.  "Kevin’s experience building high-growth technology businesses, including a market leading SSD business at flash memory pioneer SanDisk, makes him an ideal selection to fulfill Everspin’s vision of making high-endurance, fast, and persistent MRAM ubiquitous in computing applications," said Geoff Tate, Everspin's lead board director, in a statement.  "From wearables to self-driving cars to big data analytics in the data center, there is an insatiable appetite developing for low latency high endurance non-volatile memory," Conley said. "Everspin has been a MRAM technology pioneer and its spin-torque MRAM holds the potential to address this market and disrupt the traditional computational memory hierarchy.
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Release time:2017-08-28 00:00 reading:2750 Continue reading>>

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