Nexperia China Says MOSFET, Logic IC Supply Chains Complete as Independent Operations Largely in Place
  After last year’s control dispute between Wingtech and Nexperia’s Netherlands headquarters sent shockwaves through the industry, Nexperia China now says it has made significant progress in building independent operations. According to EE Times China, Wingtech Chairwoman Ruby Yang announced on May 29 that Nexperia China has largely completed the setup of its independent operating system.  Yang revealed that Nexperia China’s core management, R&D, and market teams are now fully based in China. The report notes that the company’s capacity and delivery capabilities have steadily recovered, while it continues to build a “China for China, China for Global” full-stack supply chain across wafer manufacturing, packaging and testing, and quality control.  The announcement comes as Wingtech faces mounting pressure. According to ESM China, the company said on April 29 that its auditor issued a “disclaimer of opinion” on its 2025 financial report, triggering a delisting risk warning under relevant rules.  Full-Stack Supply Chains Advance Across Key Product Lines  In terms of product layout, Nexperia China currently covers three core business lines: MOSFETs, logic ICs, and bipolar transistors, including protection devices. Yang said none of the three previously had a fully domestic, full-stack supply chain. However, according to the report, MOSFET and logic IC products have now established such supply chains.  The bipolar transistor line is being upgraded to a 12-inch platform and is expected to complete its full-stack domestic supply chain within 2026. Bipolar transistors entered small-batch mass production in March 2026, with capacity for protection devices such as ESD (Electrostatic Discharge) and TVS (Transient Voltage Suppressor) products expected to gradually come online in the second half of 2026, the report notes.  Under the plan, 19 products are expected to be ready for supply by next month, covering more than 80% of demand, the report adds. Despite the severe supply-chain fallout from last year’s Wingtech-Nexperia control dispute, the report indicates that Nexperia China has maintained large-scale delivery capabilities. Since mid-October 2025, it has shipped more than 11 billion chips to over 800 customers.  Wingtech Seeks Court Action in Nexperia Control Dispute  Meanwhile, the battle for control of Nexperia has escalated further. According to South China Morning Post, Wingtech said last week that it had filed a lawsuit in a court in China’s southern Guangdong province against Nexperia and three of its executives. The suit demands the restoration of full corporate control and 8 billion yuan, or US$1.18 billion, in compensation.  As Bloomberg notes, Wingtech asked the court to order the defendants to stop carrying out or supporting the disputed measures, including by withdrawing legal proceedings in the Netherlands and revoking a Dutch ministerial order issued last September under the Goods Availability Act. If the defendants fail to comply, Wingtech would seek the transfer of Nexperia and related subsidiaries to the company free of charge.
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Release time:2026-06-02 10:25 reading:191 Continue reading>>
SK hynix Introduces iHBM Solution, Targets HBM5 Adoption with 30% Thermal Resistance Reduction
  As thermal management emerges as a key challenge for HBM, SK hynix has unveiled its iHBM solution, which integrates cooling elements (ICEs) directly into the HBM package. The company plans to adopt the technology in next-generation products, including HBM5, according to its press release.  According to SK hynix, unlike conventional HBM designs that dissipate heat through the core die, iHBM integrates cooling elements (ICEs), made of thermally conductive, electrically non-conductive silicon-based materials, directly into the D2D PHY between HBM and GPUs, where heat is most concentrated. The company said the technology reduces thermal resistance by 30% and improves operating stability.  As highlighted by SK hynix, the iHBM solution adopts a structural approach to thermal management by creating an additional heat dissipation path within the package. It also leverages the company’s wafer-level packaging (WLP) process and proven MR-MUF technology to enable stable high-volume manufacturing.  In addition, its compatibility with existing System-in-Package (SiP) architectures allows customers to adopt the thermal solution with minimal design modifications, SK hynix adds.  In terms of future roadmap, SK hynix plans to incorporate the iHBM solution into next-generation HBM products, including HBM5, with the goal of improving the stability and efficiency of HPC systems and AI data centers.  Another Key Technology beyond Hybrid Bonding  Alongside SK hynix’s latest iHBM solution, hybrid bonding is widely seen as a key approach to addressing heat dissipation challenges in 20-stack HBM, which, as previously reported by The Elec, are expected to become increasingly difficult.  As explained in the report, hybrid bonding differs from conventional thermo-compression (TC) bonding, which connects chips through soldered micro-bumps. Instead, it bonds dielectric materials such as silicon dioxide (SiO₂) and copper through an annealing process at temperatures of roughly 200°C to 400°C.  By heating and gradually cooling copper sealed within dielectric layers, thermal expansion and vertical pressure enable direct copper-to-copper diffusion bonding without reaching copper’s melting point, the report notes, adding this approach helps reduce thermal damage to semiconductor circuits while delivering improved thermal and electrical performance.
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Release time:2026-05-27 10:42 reading:375 Continue reading>>
NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond HBM
  As AI models continue to scale, HBM may struggle to meet future memory-capacity demands, prompting industry experts to view GPU-driven storage architectures as a potential next frontier. According to The Elec, NVIDIA and Amazon are reportedly advancing storage architectures that allow GPUs to directly control storage devices such as SSDs. NVIDIA is said to plan the introduction of GPU-Initiated Direct Storage Access (GIDS) starting with its Vera Rubin AI platform, a shift that could accelerate the emergence of high-bandwidth flash (HBF), the report notes.  Citing Song Ki-hwan, a professor in the Department of System Semiconductor Engineering at Yonsei University, the report explains that GIDS goes beyond existing GPU Direct Storage (GDS) architecture. Under GDS, CPUs issue data requests to storage devices before data is transferred to GPUs. GIDS advances this by allowing GPUs to access storage directly, bypassing CPUs and DRAM.  Both GIDS and GDS aim to overcome data-transfer bottlenecks tied to traditional von Neumann computing architectures. Microsoft and AMD are also said to be exploring similar approaches. The report, citing Song, adds that traditional data-transfer methods are inefficient because CPUs are structurally limited in thread processing, while GPUs can generate tens of thousands of parallel threads. Song also notes that GPU-HBM data transfer already accounts for roughly half of total system power, strengthening the case for HBF architectures that place ultra-fast NAND closer to GPUs to address future AI bottlenecks.  GIDS Could Accelerate HBF and Expand NAND’s Role in AI Memory  The emergence of GIDS could allow NAND storage to take on a larger role in AI memory systems while easing pressure on HBM capacity. As the report notes, this shift would require higher-performance NAND flash capable of keeping pace with GPU processing speeds. One proposed approach is high-bandwidth flash (HBF), which stacks NAND flash vertically in a structure similar to HBM and connects it using through-silicon vias (TSVs).  The report notes that NAND flash offers roughly 30 times higher bit density than DRAM, enabling far greater memory capacity in a similar footprint. According to Song, combining six HBF units with two HBM units could increase GPU memory capacity more than 16 times, from 192GB to 3,120GB, potentially supporting AI models with parameter sizes around 16 times larger than current architectures.  Still, NAND flash has endurance limits, typically supporting only around 100,000 write-and-erase cycles versus DRAM’s near-unlimited write capability. As a result, HBF is seen as better suited for storing AI model parameters, which remain largely unchanged during inference and function as read-only workloads.  Meanwhile, memory makers have also been exploring GPU-driven memory architectures. According to an Edaily report last year, sources said Samsung Electronics is actively researching next-generation high-performance Z-NAND. The company is also developing GIDS technology that would allow GPUs to directly access Z-NAND-based storage devices. If implemented, GPUs would be able to access Z-NAND devices without intermediaries, potentially shortening processing times for AI workloads.
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Release time:2026-05-20 11:20 reading:802 Continue reading>>
YC Chem Reportedly First to Supply Glass Substrate Photoresists; Customer Eyes Year-End Mass Production
  South Korea’s YC Chem has reportedly become the first in the industry to supply photoresists for glass substrates. According to The Elec, sources say the company is supplying i-line photoresist, stripper, and developer materials for glass substrates to a customer after receiving a purchase order (PO) following qualification tests.  As supply of related materials begins to ramp up, commercialization of glass substrates also appears to be drawing closer, the report notes. Current shipments are intended for the customer’s prototype production, with material supply volumes expected to increase gradually as the customer moves toward mass production from the end of this year.  The company is also seeking additional customers. According to the report, it is currently in discussions with more than three companies regarding the supply of glass substrate materials. With some firms, sample testing is underway for negative photoresists and glass substrate coating materials.  YC Chem has also supplied prototype coating materials for glass substrates to customers. These materials are intended to minimize cracking and warpage caused by differences in thermal expansion coefficients (CTE) and thermal conductivity between glass and copper. According to the report, the products are currently undergoing qualification testing.  The report notes that the coating materials are used in embedding-type glass substrates, which integrate circuits and passive components directly within the glass substrate itself.  Key Requirements for Photoresists in Glass Substrate Manufacturing  As the report points out, the glass substrate photoresist supplied by YC Chem is based on i-line technology, which uses a 365-nanometer (nm) mercury lamp wavelength in the lithography process. Notably, the report points out that, unlike extreme ultraviolet (EUV) photoresists used in advanced semiconductor manufacturing, glass substrate production places greater emphasis on thicker film thickness and strong etch resistance.  In particular, the report states that through-glass via (TGV) processes require strong chemical durability and high etch resistance during hole formation and copper plating. As a result, demand is increasing for longer-wavelength lithography materials such as i-line and krypton fluoride (KrF)-based photoresists.  In South Korea, Samyang NC Chem is also developing photoresist materials for glass substrates. The report adds that the company has supplied samples to more than two customers and is reportedly aiming for mass production next year.  As major companies accelerate glass substrate development, securing stable material supplies is becoming increasingly important. A January Chosun Biz report said Absolics is diversifying suppliers by adding a domestic partner for glass substrate photoresists, reducing reliance on Japan’s TOK, while also reviewing process dualization for TGV and plating processes through additional collaborators.
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Release time:2026-05-18 13:05 reading:612 Continue reading>>
ARM CEO Says Agentic AI May Drive CPU Core Counts to 512 as GPU-CPU Ratios Become Less Relevant
  The rise of agentic AI is fueling fresh debate over the future GPU-to-CPU balance in AI systems, with Arm CEO Rene Haas now weighing in on the discussion. According to a transcript published by Investing.com, Haas said that while CPUs may not outnumber GPUs on a chip basis, they could from a core-count perspective.  Haas noted that overall CPU demand is likely to increase significantly as agentic AI scales, with data centers potentially requiring more than four times today’s CPU capacity. He said this could create a data center CPU market opportunity exceeding US$100 billion by 2030.  At the same time, Haas emphasized that the industry is seeing not only an explosion in overall CPU demand, but also rapid growth in the number of cores per CPU. According to Haas, many agentic AI workloads involve independent jobs, flows, or batches running on dedicated CPU cores, increasing the need for higher-core-count processors.  Haas used Blackwell, Rubin, and other large AI accelerators as examples, noting that these chips are already approaching reticle limits, meaning their size is constrained by the maximum area a lithography mask can print. In contrast, he said CPU core counts could still double or even quadruple over the coming years.  Haas noted that the Arm AGI CPU already features 136 cores, significantly higher than many competing offerings. Looking ahead, he said the industry is likely to move toward 256-core and even 512-core CPU designs. He added that such high-core-count architectures play to Arm’s strengths, as efficiency per core becomes increasingly critical at larger scales.  Mydrivers notes that AMD and Intel are moving in a similar direction. AMD’s 2nm Zen 6-based EPYC processors are already expected to reach up to 256 cores with SMT multithreading support, while Intel’s all-E-core Xeon processors have reached 288 cores, with the next generation expected to scale to as many as 512 cores.  Regarding the Arm AGI CPU launched at the company’s Arm Everywhere event last quarter, Haas said customer response has been “very strong.” He added that customer demand across fiscal 2027 and fiscal 2028 has already exceeded US$2 billion, more than double the level projected at launch.
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Release time:2026-05-11 13:48 reading:564 Continue reading>>
Apple Reportedly Keeps 2nm 5G Modem Orders with TSMC Amid Intel Cooperation Signals
  While recent market chatter has focused on a potential shift by Apple between longtime foundry partner TSMC and Intel, the Economic Daily News, citing industry sources, reports that the Cupertino-based company remains heavily dependent on the Taiwanese foundry giant, as it plans to place its entire in-house 5G modem orders with TSMC, leveraging its 2nm process technology.  The report suggests that Apple’s self-developed 5G modem chips are expected to power future iPhone, iPad, and Apple Watch devices, replacing modems from Qualcomm. The volume used across its product lineup is projected to reach hundreds of millions of units, the report adds.  Notably, Apple’s iPhone 17 lineup is expected to be the last to ship with Qualcomm Incorporated’s 5G modems, as the company moves toward a full transition to its in-house C2 baseband chip across all iPhone 18 models, according to Wccftech.  The C2 development builds on Apple’s earlier in-house modem effort. Apple’s C1, first introduced in early 2025 with the iPhone 16e, marked its most complex chip system to date, integrating a 4nm baseband modem and a 7nm transceiver, according to earlier reporting from Reuters. The Economic Daily News further reports that Apple Inc.’s in-house C2 5G modem is expected to add full mmWave support—addressing the Sub-6 GHz limitation of its predecessor—while also incorporating satellite connectivity.  Supply chain sources cited in the Economic Daily News report say TSMC has already secured foundry orders for Apple’s modem chips. Its back-end testing partner is also reportedly preparing for higher demand, with around 600 test systems being procured, as capacity is set to ramp from 2027.  Apple’s Chip Tug-of-War: TSMC vs Intel  Though claims of an Apple order shift to Intel remain unconfirmed, and any such move would not signal a departure from TSMC, cooperation between Apple and Intel appears to be warming. According to The Wall Street Journal, the two companies have reportedly reached a preliminary agreement for Intel to manufacture some of the chips powering Apple devices.  The two sides have been engaged in intensive talks for more than a year, with a formal deal said to have been hammered out in recent months, the report adds.  In parallel, Commercial Times reported earlier that Apple is evaluating Intel’s 18A-P process for its M-series chips. Looking further ahead, The New 7 reports that the first Intel-manufactured low-end M-series chips could emerge as early as mid-2027 under contract production, likely targeting entry-level Macs or iPads.  As highlighted by The Wall Street Journal, Apple’s reported outreach to Intel may reflect growing supply chain pressures, as the Cupertino firm—long TSMC’s top customer—faces tightening access to advanced manufacturing capacity amid surging demand from NVIDIA and other AI chip designers.  Intel previously played a central role in powering Apple’s Mac lineup, before Apple transitioned in 2020 to its own Arm-based custom chips, the report points out.
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Release time:2026-05-11 11:12 reading:574 Continue reading>>
TSMC, Sony to Form JV for Image Sensors, Including New Production Lines for AI and Automotive Use
  As TSMC has decided to upgrade its 2nd Kumamoto fab to 3nm, the foundry giant is also exploring to secure more opportunities for its mature nodes in Japan. According to its press release on May 8, Sony and TSMC announced the signing of a non-binding memorandum of understanding (MOU) to establish a strategic partnership focused on the development and manufacturing of next-generation image sensors.  Notably, under the proposed framework, the two companies plan to form a joint venture (JV), with Sony serving as the majority and controlling shareholder. The JV is expected to build development and production lines at Sony’s newly constructed fab in Koshi City, Kumamoto Prefecture.  TSMC said that beyond manufacturing expansion, the partnership is also aimed at exploring emerging opportunities in physical AI applications, including automotive and robotics.  Through this collaboration, Sony will contribute its deep expertise in image sensor design, while TSMC will bring its advanced process technology and large-scale manufacturing capabilities. Both sides aim to combine their respective strengths to further enhance the performance and competitiveness of future image sensor technologies.  The move aligns with an April Reuters report, which noted that Japan’s Ministry of Economy, Trade and Industry (METI) has confirmed that the Japanese government will provide subsidies of up to ¥60 billion (approximately US$380 million) to Sony Semiconductor Solutions Corporation for the construction of an image sensor facility in Kumamoto Prefecture, western Japan.  Sony is a long-time customer of TSMC. As previously reported by Commercial Times, TSMC’s first Kumamoto fab—entering mass production in late 2024—supplies logic chips to Sony and DENSO, using 22/28nm and 12/16nm process technologies.  Separately, Sony has recently begun restructuring efforts, including a spin-off of its television business. Its CIS (image sensor) unit is also facing rising competitive pressure, as Samsung Electronics continues to expand its share in supplying image sensors for Apple, prompting Sony to seek new growth momentum in the segment, Commercial Times added.
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Release time:2026-05-09 10:16 reading:837 Continue reading>>
TSMC Hints at Potential Further U.S. Expansion; Industry Sources Reportedly See Up to US$250B Investment
  As TSMC continues expanding its U.S. footprint, comments from Cliff Hou, TSMC Senior Vice President and Deputy Co-COO, have caught industry attention. According to Commercial Times, Hou said at the 2026 SelectUSA Investment Summit that the company “is prepared for growth from any new business opportunities,” remarks the market has interpreted as signaling potential further expansion of TSMC’s U.S. investments. TSMC’s total U.S. investment currently stands at US$165 billion.  Commercial Times notes that supply chain developments show chip equipment suppliers have also begun establishing U.S. subsidiaries to support TSMC. Industry sources added that TSMC’s total U.S. investment could reach as much as US$250 billion, with the company expected to replicate the Hsinchu Science Park cluster model in Phoenix.  Meanwhile, Economic Daily News reported that TSMC’s first Arizona fab entered mass production in 4Q24, while its second fab has already been completed and is expected to begin 3nm mass production in the second half of 2027. TSMC previously said construction of its third Arizona fab is already underway, while permits are being sought for a fourth fab and its first advanced packaging facility in the state. The report also noted that TSMC has acquired a second large parcel of land near its existing Arizona site to support future expansion plans.  Although TSMC’s U.S. fabs are more costly, capacity remains in strong demand, with previous reports indicating that customers had already reserved capacity at all four Arizona fabs, as noted by Economic Daily News. Institutional investors said that, for process technologies below 2nm, TSMC’s related capacity ratio between Taiwan and the U.S. is expected to reach roughly 7:3 by 2030.  TSMC Reshapes Board Amid Global Expansion  In addition, TSMC has also recently adjusted its board structure. According to Commercial Times, the company plans to revise its corporate charter by increasing the number of board seats from the current seven to ten directors to nine to twelve, with the proposal set to be discussed at the shareholders’ meeting on June 4.  The move reflects TSMC’s response to the rapidly changing global business environment and is intended to provide greater flexibility in recruiting directors from diverse professional backgrounds, the report said. It also noted that, as TSMC rapidly expands overseas and continues increasing its U.S. investments, the board will need more members with expertise in international supply chains, geopolitics, and U.S. policy.
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Release time:2026-05-07 13:22 reading:473 Continue reading>>
Apple Reportedly Eyes Samsung, Intel U.S. Foundry for Core Chips Amid TSMC Constraints, Supply Diversification
  Apple is reportedly weighing the possibility of having some of its core device chips manufactured by Samsung and Intel. According to Bloomberg, citing sources, the company has held preliminary discussions on using the two as alternative production partners for its main processors—potentially providing a second sourcing option alongside its longstanding supplier, TSMC.  Sources say the company has held early-stage discussions with Intel about leveraging its foundry services, while Apple executives have also visited a Samsung facility under construction in Texas that is expected to produce advanced chips.  That said, the report notes that neither effort has led to any orders so far. Engagements with both suppliers remain at a preliminary stage, as Apple continues to have reservations about adopting non-TSMC manufacturing technologies.  One of the key drivers behind Apple’s potential shift is supply constraints at TSMC, according to Bloomberg. As the report notes, Apple executives addressed the issue during the company’s quarterly earnings call last week, indicating that limited chip availability for iPhone and Mac devices is currently weighing on growth.  In early 2026, Tim Cook identified access to advanced-node manufacturing as the main bottleneck for Apple’s iPhone output, according to CNBC. He noted that production is constrained by limited capacity for the company’s A-series and M-series system-on-chip (SoC) chips, which are fabricated on TSMC’s 3nm process.  In addition, it also aims to maintain at least two suppliers for key components, allowing Apple to strengthen its negotiating leverage on pricing while reducing the risk of supply disruptions, Bloomberg adds.  Apple’s Reported Supplier Talks May Open Door for Intel Comeback, Samsung Gains  Apple’s talks with both companies reportedly began before the most recent supply constraints emerged. As Bloomberg notes, collaborating with Intel could offer an added advantage, potentially strengthening Apple’s ties with the Donald Trump administration. As for Samsung, the report indicates that it has already been working on supplying more peripheral components for Apple’s devices, including power management parts.  In an August 2025 press release, Apple also announced a partnership with Samsung to co-develop a new chip manufacturing technology at Samsung’s Austin fab. Citing industry sources, Business Korea adds that the chip Samsung is expected to produce will likely be used as an image sensor in future iPhones and other Apple products.  Separately, industry momentum appears to be building around Intel’s foundry push. According to Commercial Times, major tech firms including Google and Apple are weighing a shift to Intel’s foundry. The report adds that Apple’s M-series chips are evaluating Intel’s 18A-P node.  Apple’s potential shift could provide a boost to both Samsung and Intel. As the report notes, securing external customers for its foundry business is central to Intel’s turnaround strategy under CEO Lip-Bu Tan. Winning Apple as a client would mark a major milestone for Tan and could help draw in additional business. Samsung, meanwhile, would also stand to gain significantly from an endorsement by Apple.
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Release time:2026-05-06 14:44 reading:462 Continue reading>>
NOVOSENSE Launches Next-Generation Isolated CAN Transceiver NSI1150, Supporting ±70V Bus Fault Protection and Higher Data Rates
  NOVOSENSE today announced the launch of its new industrial-grade isolated CAN transceiver, the NSI1150 series. Built on NOVOSENSE's third-generation isolation technology, the device delivers ±70V bus fault protection and up to ±150kV/μs (typical) common-mode transient immunity (CMTI). Compared to the previous generation (NSI1050), the NSI1150 achieves a comprehensive improvement in reliability and noise immunity. It also integrates NOVOSENSE's proprietary CAN FD transceiver, supporting communication speeds of up to 5 Mbps.  The NSI1150 is available in multiple package options, including SOW16, SOW8, SOP8, SOWW8, and DUB8, addressing diverse design requirements. It is well suited for high-voltage, high-noise, multi-node applications such as industrial automation and control, energy and power systems, as well as communications and servers.  Reliability Upgrade for Harsh Environments  The NSI1150 delivers industry-leading reliability and robustness, featuring a high CMTI of ±150kV/μs (typical) and ±70V bus fault protection, enabling it to effectively handle strong electromagnetic interference and ground potential differences in demanding environments.  In addition, all pins support ±6kV HBM ESD protection and 10kV surge capability across the isolation barrier, ensuring stable communication even under extreme conditions. The device offers multiple isolation ratings—3 kVRMS, 5 kVRMS, and 7.5 kVRMS—to meet stringent safety requirements across various applications, reinforcing system protection in critical sectors such as industrial automation and energy infrastructure.  Multiple Package Options for Flexible Design  The NSI1150 is offered in five mainstream package options—SOW16, SOW8, SOP8, SOWW8, and DUB8—accommodating different space constraints and safety requirements. Among them, the newly introduced SOWW8 wide-body package provides up to 15 mm creepage distance, making it ideal for applications with strict creepage requirements, such as photovoltaic systems, EV charging stations, and industrial power supplies.  This extended creepage distance simplifies safety certification processes and enables more flexible layout design for high power density systems. The diversified package portfolio further enhances design flexibility and accelerates time-to-market.  "Isolation+" Portfolio Setting Industry Benchmark  Leveraging its deep expertise and technological leadership in isolation, NOVOSENSE offers a comprehensive "Isolation+" portfolio, including digital isolators, isolated sensing, isolated interfaces, isolated power, and isolated drivers.  NOVOSENSE is building a robust safety foundation for high-voltage systems with its full "Isolation+" ecosystem:  "+" stands for enhanced safety: NOVOSENSE products deliver safety levels exceeding basic isolation standards, and build a more reliable system isolation safety boundary for customers' systems.  "+" stands for full product ecosystem: With mature capacitive isolation technology IP as the cornerstone, expand into a complete product portfolio to provide one-stop isolation solutions.  "+" stands for in-depth application empowerment: Meet the emerging needs of scenarios including electric vehicle high-voltage platforms, high-power photovoltaic-storage-charging systems, and high-integration, high-efficiency AI server power supplies, enabling system-level safety, reliability and efficiency.  With its comprehensive "Isolation+" product strategy—anchored by core technology IP and a full ecosystem—NOVOSENSE continues to set the benchmark in isolation semiconductors, delivering one-stop isolation solutions to customers worldwide.  Previous:
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Release time:2026-04-24 10:58 reading:717 Continue reading>>

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