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<span style='color:red'>Imec</span>, CEA-Leti Form AI and Quantum Computing Hub

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Imec, CEA-Leti Form AI and Quantum Computing Hub

Two of Europe’s key electronics and nanotechnologies research institutes — imec in Belgium and CEA-Leti in France — will collaborate to develop a European hub for artificial intelligence and quantum computing.As security and privacy issues rise up the agenda in almost every organization, the race is on to process more at the edge and put more intelligence at endpoints. For electronics systems design, most of the major chip companies now offer or are developing deep learning and edge AI devices or intellectual property. The edge AI devices are often complete computer sub-systems displaying intelligent behavior locally on the hardware devices (chips), analyzing their environment and taking required actions to achieve specific goals.Edge AI is considered now to hold the promise of solving many societal challenges — from treating diseases that cannot yet be cured today, to minimizing the environmental impact of farming. Decentralization from the cloud to the edge is a key challenge of AI technologies applied to large heterogeneous systems. This requires innovation in the components industry with powerful, energy-guzzling processors.This is where imec and CEA-Leti hope to develop a European center of excellence. The two organizations signed a memorandum of understanding during the state visit of French president Emmanuel Macron to Belgium, laying the foundation for a strategic partnership in AI and quantum computing, two key strategic value chains for European industry, to strengthen European strategic and economic sovereignty.The joint efforts of imec and CEA-Leti underline Europe’s ambition to take a leading role in the development of these technologies. The research centers’ increased collaboration will focus on developing, testing and experimenting neuromorphic and quantum computing — and should result in the delivery of a digital hardware computing toolbox that can be used by European industry partners to innovate in a wide variety of application domains — from personalized healthcare and smart mobility to the new manufacturing industry and smart energy sectors."The ability to develop technologies such as AI and quantum computing — and put them into industrial use across a wide spectrum of applications — is one of Europe’s major challenges," said Luc Van den hove, president and CEO of imec, in a press statement. "Both quantum and neuromorphic computing (to enable artificial intelligence) are very promising areas of innovation, as they hold a huge industrialization potential.” Van den hove said a stronger collaboration in these domains between imec and CEA-Leti would help to speed up the technologies’ development time, providing them with the critical mass needed to create faster impact.Emmanuel Sabonnadière, CEA-Leti CEO, said the collaboration with imec as well as previous innovation-collaboration agreements with Germany's the Fraunhofer Group for Microelectronics "will focus all three institutes to the task of keeping Europe at the forefront of new digital hardware for AI, HPC and cyber-security applications.”Imec and CEA-Leti are inviting partners from industry as well as academia to join them and benefit from access to the research centers’ technology — enabling a much higher degree of device complexity, reproducibility and material perfection while sharing the costs of precompetitive research.

Key word：

AI

Release time：2018-11-22 00:00 reading：1185 Continue reading>>

<span style='color:red'>Imec</span> and CEA-Leti join forces on Artificial Intelligence and Quantum Computing

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Imec and CEA-Leti join forces on Artificial Intelligence and Quantum Computing

The Belgian research centre imec and the French research institute CEA-Leti, two leading research and innovation hubs in nanotechnologies for industry, have signed a memorandum of understanding (MoU) that lays the foundation of a strategic partnership in the domains of Artificial Intelligence and quantum computing.The joint efforts of imec and CEA-LETI underline Europe’s ambition to take a leading role in the development of these technologies and this increased collaboration will focus on developing, testing and experimenting neuromorphic and quantum computing – and should result in the delivery of a digital hardware computing toolbox that can be used by European industry partners to innovate in a wide variety of application domains – from personalised healthcare and smart mobility to the new manufacturing industry and smart energy sectors.Edge Artificial Intelligence (eAI) commonly refers to computer systems that display intelligent behavior locally on the hardware devices (e.g chips). They analyse their environment and take the required actions to achieve specific goals.Edge AI is poised to become a key driver of economic development. And, even more importantly perhaps, it holds the promise of solving many societal challenges – from treating diseases that cannot yet be cured today, to minimising the environmental impact of farming.Decentralisation from the cloud to the edge is a key challenge of AI technologies applied to large heterogeneous systems. This requires innovation in the components industry with powerful, energy-guzzling processors.“The ability to develop technologies such as AI and quantum computing – and put them into industrial use across a wide spectrum of applications – is one of Europe’s major challenges. Both quantum and neuromorphic computing (to enable artificial intelligence) are very promising areas of innovation, as they hold a huge industrialisation potential,” said Luc Van den hove, president and CEO of imec.“A stronger collaboration in these domains between imec and CEA-Leti, two of Europe’s leading research centers, will undoubtedly help to speed up the technologies’ development time: it will provide us with the critical mass that is required to create more – and faster – impact, and will result in plenty of new business opportunities for our European industry partners.”“Two European microelectronics pioneers today are joining forces to raise the game in both high-performance computing and trusted AI at the edge, and ultimately to fuel European industry success through innovations in aeronautics, defence, automobiles, Industry 4.0 and health care,” said Emmanuel Sabonnadière, Leti CEO. “This collaboration with imec following earlier innovation-collaboration agreements with the Fraunhofer Group for Microelectronics of the Fraunhofer-Gesellschaft, the largest organization for applied research, will focus all three institutes to the task of keeping Europe at the forefront of new digital hardware for AI, HPC and Cyber-security applications.”Imec and CEA-Leti are inviting partners from industry as well as academia to join them and benefit from access to the research centers’ state-of-the-art technology with proven reproducibility – enabling a much higher degree of device complexity, reproducibility and material perfection while sharing the costs of precompetitive research.

Key word：

AI

Release time：2018-11-21 00:00 reading：1022 Continue reading>>

<span style='color:red'>Imec</span> and ASML announce EUV lithography collaboration

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Imec and ASML announce EUV lithography collaboration

imec, the research and innovation hub in nanoelectronics and digital technologies, and ASML, a leading developer of lithographic equipment, have announced the next step in their ongoing and extensive collaboration.The two are looking to accelerate the adoption of EUV lithography for high-volume production, including the current latest available equipment for EUV (0.33 Numerical Aperture, NA). Moreover, they are looking to explore the potential of the next-generation high-NA EUV lithography to enable printing of even smaller nanoscale devices advancing semiconductor scaling towards the post 3 nanometer Logic node. As a result they have established a joint high-NA EUV research lab.In 2014, they created a joint research centre, the Advanced Patterning Center, to optimize lithography technology for advanced CMOS integration and to prepare the ecosystem to support advance patterning requirements. The next stage of this co-operation will see the installation of ASML’s most advanced and high-volume production dedicated EUV scanner (NXE:3400B) in imec’s cleanroom.Using imec’s infrastructure and advanced technology platforms, researchers and partner companies will be able to pro-actively analyse and solve technical challenges such as defects, reliability and yield, and as such help to accelerate the EUV technology’s industrialisation.With a 250W light source, ASML’s newest EUV system throughput will be more than 125 wafers per hour, one of the industry’s most important requirements for high-volume production. The NXE:3400B will also be equipped with the latest alignment and leveling sensors, to enable optimal process control at this high throughput. This will facilitate the overlay matching of the NXE:3400B to that of the latest immersion scanner, NXT:2000i, that will also be installed in imec’s cleanroom in 2019. In addition, ASML and imec will expand the metrology capability with new ASML YieldStar optical metrology and ASML-HMI Multi-electron beam metrology equipment, allowing more accurate and faster evaluation of nanoscale structures.The joint high-NA EUV research lab will see researchers from both organisations experiment with the next generation of EUV lithography at higher NA. Systems with a higher NA project the EUV light onto the wafer under larger angles, improving resolution, and enabling printing of smaller features. More specifically, the new high-NA EUV system, EXE:5000, that will be installed in the joint research lab, will have an NA of 0.55 instead of 0.33 in current NXE:3400 EUV systems.Already, the first joint scientific projects to facilitate the introduction of high-NA EUV, are ongoing. In the joint research lab, ASML and imec will perform research on the manufacturing of the most advanced nanoscale devices by high-NA EUV and assist the ecosystem of equipment and material suppliers to prepare for the introduction of high-NA EUV technology to the industry.Commenting Luc Van den hove, President and CEO of imec, said: “The new EUV scanners and ASML metrology equipment will allow our industry partners to perform collaborative research on the most advanced and industry relevant lithography and metrology equipment. ASML and imec have a nearly 30 year long tradition of joint research, leading to breakthrough patterning research to advance the semiconductor industry roadmap.”

Key word：

Imec,ASML

Release time：2018-10-26 00:00 reading：1341 Continue reading>>

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imec’s research hub raises €117million to invest in start-up innovations

imec’s research and innovation hub, imec.xpand, which specialises in nanoelectronics and digital technology, has closed its first fund at €117million in committed capital.The amount raised exceeds the initial target of €100m and imec believes, positions imec.xpand as a “major player” in the deep tech venture capital ecosystem.The fund targets ambitious tech start-ups for whom imec knowledge, expertise and infrastructure can play a determining role in their success.Imec.xpand aims to engage with companies at an early stage, at the same time as reserving sufficient financial resources to support the selected ventures from the early stages of development all the way through the commercialisation of their product.The idea is that this will allow start-ups to focus on developing a technology and on building a business, rather than spending all their time and energy on securing the next round of financing. imec believes this philosophy will increase the speed at which ventures can enter the market and help create the technology leaders of tomorrow that will generate above average financial returns for the investors in imec.xpand.

Key word：

Instant news

Release time：2018-09-17 00:00 reading：994 Continue reading>>

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imec shows integrated 5G chip directions

To fulfill the promise of the Internet of Things (IoT), the world needs low-cost high-bandwidth radio-frequency (RF) chips for 5th-generation (5G) internet technology. Despite standards not being completely defined yet it is clear that 5G hardware will have to be more complex than 4G kit, because it will have to provide a total solution that is ultra-reliable with at least 10 Gb/second bandwidth. A significant challenge remains in developing new high-speed transistor technologies for RF communications with low power to allow IoT “edge” devices to operate reliably off of batteries.At the most recent Imec Technology Forum in Antwerp, Belgium, Nadine Collaert, Distinguished MTS of imec, discussed recent research results from the consortium’s High-Speed Analog and RF Program. In addition to working on core transistor fabrication technology R&D, imec has also been working on system-technology co-integration (STCO) and design-technology co-integration (DTCO) for RF applications.Comparing the system specifications needed for mobile handsets to those for base-stations, transmitter power consumption should be 10x lower, while the receiver power consumption needs to be 2x lower. Today using silicon CMOS transistors, four power amplifiers alone consume 65% of a transmitter chip’s power. Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) built using compound semiconductors such as gallium-arsenide (GaAs), gallium-nitride (GaN), or indium-phosphide (InP) provide excellent RF device results. However, compared to making CMOS chips on silicon, HBT and HEMT manufacturing on compound semiconductor substrates is inherently expensive and difficult.Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) both rely upon the precise epitaxial growth of semiconductor layers, and such growth is easier when the underlying substrate material has similar atomic arrangement. While it is much more difficult to grow epi-layers of compound semiconductors on silicon wafers, imec does R&D using 300-mm diameter silicon substrates with a goal of maintaining device quality while lowering production costs. The Figure shows cross-sections of the two “tracks” of III-V and GaN transistor materials being explored by imec for future RF chips.III-V on Silicon and GaN-on-Silicon RF device cross-sections, showing work on both Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) for 5G applications. (Source: imec)Imec’s High-Speed Analog/RF Program objectives include the following:High-speed III-V RF devices using low-cost, high-volume silicon-compatible processes and modules,Co-optimization with advance silicon CMOS to reduce form factor and enable power-efficient systems with higher performance, andTechnology-circuit design co-optimization to enable complex RF-FEM modules with heterogeneous integration.5G technology deployment will start with speeds below 6GHz, because technologies in that range have already been proven and the costs are known. However, after five years the frequency will change to the “mm-wave” range with the first wavelength band at ~28GHz. GaN material with a wide bandgap and high charge-density has been a base-station technology, and it could be an ideal material for low-power mm-wave RF devices for future handsets.This R&D leverages the III-V on silicon capability that has been developed by imec for CMOS:Photonic integration. RF transistors could be stacked over CMOS transistors using either wafer- or die-stacking, or both could be monolithically co-integrated on one silicon chip. Work on monolithic integration of GaN-on-Silicon is happening now, and could also be used for photonics where faster transistors can improve the performance of optical links.

Key word：

5G

Release time：2018-07-13 00:00 reading：1272 Continue reading>>

Cadence, <span style='color:red'>Imec</span> Disclose 3-nm Effort

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Cadence, Imec Disclose 3-nm Effort

　　SAN JOSE, Calif. — Cadence Design Systems and the Imec research institute disclosed that they are working toward a 3-nm tapeout of an unnamed 64-bit processor. The effort aims to produce a working chip later this year using a combination of extreme ultraviolet (EUV) and immersion lithography.　　So far, Cadence and Imec have created and validated GDS files using a modified Cadence tool flow. It is based on a metal stack using a 21-nm routing pitch and a 42-nm contacted poly pitch created with data from a metal layer made in an earlier experiment.　　Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec hopes to optimize the process to use a single pass in the EUV scanner. Ultimately, fabs may migrate to a planned high-numerical-aperture version of today’s EUV systems to make 3-nm chips.　　The 3-nm node is expected to be in production as early as 2023. TSMC announced in October plans for a 3-nm fab in Taiwan, later adding that it could be built by 2022. Cadence and Imec have been collaborating on research in the area for two years as an extension of past efforts on 5-nm devices.　　“We made improvements in our digital implementation flow to address the finer routing geometry … there definitely will be some new design rules at 3 nm,” said Rod Metcalfe, a product management group director at Cadence, declining to provide specifics. “We needed to get some early visibility so when our customers do 3 nm in a few years, EDA tools will be well-defined.”　　Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs used in today’s 16-nm and finer processes.　　“Our work on the test chip has enabled interconnect variation to be measured and improved and the 3-nm manufacturing process to be validated,” said An Steegen, executive vice president for semiconductor technology and systems at Imec, in a press statement.　　The research uses Cadence Innovus Implementation System and Genus Synthesis tools. Imec is using a custom 3-nm cell library and a TRIM metal flow. The announcement of their collaboration comes one day after Imec detailed findings of random defectsimpacting 5-nm designs.

Key word：

Cadence

Release time：2018-03-01 00:00 reading：1088 Continue reading>>

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4DS Enlists IMEC to Advance ReRAM

　　A resistive RAM (ReRAM) company that recently claimed its storage-class memory technology was as fast as DRAM is collaborating with IMEC to develop a production-compatible process.　　4DS Memory Limited announced in June it had successfully tuned its Interface Switching ReRAM cell architecture to storage class memory with read speeds comparable to DRAM without needing speed-limiting error correction. Last year, the company announced it had scaled these cells to 40nm, but until now these cells have been fabricated with R&D process tools that differ from those used for high-density, high-volume memories in production fabs.　　The 4DS Interface Switching ReRAM technology is area-based as cell currents scale with cell area and the wiring therefore scales accordingly, the company says, and the technology is also based on well-understood physics and chemistry.　　In a telephone interview with EE Times, 4DS CEO Guido Arnout said now that after scaling down to 40nm and showing both predictability and repeatability, 4DS felt it was the right time to approach IMEC with its unique cell. The collaboration will demonstrate 4DS' production backend-of-line (BEOL) process on IMEC's CMOS megabit memory vehicle processed at 300mm wafers to make 1Mb devices, he said.　　Arnout said flash is getting cheaper by the day, so competing with it means undercutting prices significantly. 4DS, however, sees a gap between flash and DRAM for another storage-class memory. “The space between flash and DRAM is huge," he said.　　As one of the leading microelectronics R&D organizations in the world, IMEC is in a strong position to help 4DS tweak its technology for finer geometries and learn everything it can about its cell in terms of yield, speed and endurance for commercial production, Arnout said. "We can't cut corners because we don't want to fail," he said. "If we cut corners, we won't get the answers."　　Doing such work in a research foundry concept is an efficient solution, said Lode Lauwers, IMEC's vice president of business development and sales, as these projects build the confidence and the level of maturity by which potential fabs will consider adopting such processes.　　“Fabs introduce new materials all the time, but they only do so if one has sufficiently demonstrated the prevailing properties and addressed the potential side effects to assure that no showstoppers occur," Lauwers said. “Assessing those options as complete as possible in the R&D phase is one key element in IMEC's programs."　　It's critical that emerging memories continue to use existing materials, tools and processes, Lauwers said. Nearly all new emerging memories — be it magnetic, resistive or phase change — build on the properties of new materials or material combinations. “These days, more than half of Mendelejev's table is under investigation to create material systems based on multiple components for experiments in memory process steps, which is impressive," Lauwers said. "Of course, with new materials comes the need to develop new processes, fab handling, integration concepts, and tooling."　　Lauwers said “healthy conservatism" has driven the industry's progress. “If one could realize the properties of functionality with a known system, that would definitely always be the preferred option," he said.　　From a research perspective, however, tackling fundamental challenges means rethinking what you have, understanding its limitations, and discovering new areas, including new materials, that have a promise to overcome those limitations, he said.　　ReRAM, as well as MRAM, are still considered emerging technologies. “They are at the eve of breakthrough, but still subject of many intensive research and development projects, even if those projects are already ongoing for many years," Lauwers said.　　Jim Handy, principal analyst with Objective Analysis, said IMEC has an advantage because of its wide array of sponsors that enable it to afford better equipment and justify having a large number of tools on hand that a commercial production environment can't justify. At the same time, it's essential that it take an emerging technology the next step, making sure it can be affordably produced with available tools and processes, he added.　　“This is to make sure this is a production worthy process," Handy said. “You can do things in an R&D fab that would bring a production environment to its knees."　　Handy said the fact that Intel has been calling its 3D Xpoint technology ReRAM is probably what's renewed the industry's interest in ReRAM, which has been around a long time, as has 4DS. “This is the first time [4DS has] shown earnest effort to turn their technology into something that's production worthy," Handy.

Key word：

4DS, IMEC,ReRAM

Release time：2017-12-04 00:00 reading：963 Continue reading>>

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Engineering needs to be promoted more effectively at schools, says IMechE

　　School students have little exposure or understanding of engineering, which is leading most to choose subjects which effectively rule out this career path early in their schooling, according to a report from the Institution of Mechanical Engineers.　　The report – We think it's important but don't quite know what it is: The Culture of Engineering in Schools – says that, although students have a vague sense of engineering’s value, its low visibility in schools means they do not feel informed or confident enough to consider it as a future career. The report also notes that teachers and career professionals lack the time, knowledge and resources to communicate the breadth of career opportunities to students.　　Peter Finegold, the IMechE’s head of education and skills, said: “The report’s findings show positive attitudes and appreciation of engineering among students, parents, teachers and school governors alike. However, few schools are integrating engineering into their teaching and the wider school culture. This is undoubtedly detrimental; not just to the future of pupils in these schools, but also to UK society more generally.”　　The report, the third in a series in which the IMechE looks at engineering in schools, calls for the Government to rethink how engineering is presented to future generations, especially girls.　　“This lack of exposure to engineering has led to students developing a vague and incoherent understanding of the profession, its career opportunities and what it does for society,” said Finegold. “We accept that Government is unlikely to change the curriculum fundamentally or introduce engineering as a standalone school subject. Therefore, we recommend that the socially beneficial, problem-solving aspects of engineering are integrated into the existing curriculum, particularly in science and technology subjects, enhancing young people’s exposure to engineering and its world-changing potential.”　　The report has nine key recommendations:　　Government should establish a working group of leading educationalists and other stakeholders to examine innovative ways in which engineering can be integrated into the curriculum;Government to appoint a National Schools Engineering Champion to provide an effective communication channel between schools, Government and industry;National Education Departments to advocate curricula that reflect the ‘made world’ to modern society, including reference to engineering in maths and D&T;National Education Departments to promote a problem based approach to learning;Schools to appoint an Engineering and Industry Leader within their senior leadership team;Schools to appoint an Industry School Governor to support the Engineering and Industry Leader and embed employer relationships within the school;Schools to implement a robust careers strategy, using benchmarks set out in the Gatsby Foundation Good Career Guidance;The engineering community to agree a unified message about engineering, stressing creative problem-solving and the social benefits of the profession;The engineering community to provide students with the opportunity to take part in activities that explore the political, societal and ethical aspects of technology.　　Finegold concluded: “As 2018 has been designated the ‘Year of Engineering’, with support across five Government departments, we believe it is time Government, as part of its future industrial strategy, ensures engineering is placed at the heart of our education system.”

Key word：

IMechE

Release time：2017-11-27 00:00 reading：1053 Continue reading>>

Trade news

‘Key’ 5G building blocks launched by imec

　　Two building blocks launched by Belgian research centre imec are said to be key for future 5G applications. The first is a fast and compact successive approximation A/D converter for consumer electronics applications operating at frequencies of less than 6GHz. The other blocks is a 60GHz front-end with RF phase shifting and on-chip transmit-receive switching. This block is intended to use in 5G fixed wireless access and small cell backhaul applications.　　Wim Van Thillo, imec’s programme director for perceptive systems, said: “Our portfolio includes record-breaking A/D converters, reconfigurable low-noise frequency synthesisers, millimetre wave phased array transceivers, antenna modules and more. These building blocks show state-of-the art performance, excel in low-power operation and are low cost by leveraging scaled CMOS technologies.”　　The A/D converter, pictured, which has core area of 350 x 325?m, is fabricated using a 16nm CMOS process. Dynamic power consumption is said to be 3.6mW at 300Msample/s, with a signal to noise and distortion ratio of 70.2dB at 204Msample/s.　　Meanwhile, the 60GHz RF front-end features eight way calibration-free beamforming to support a large number of antennas. This, says imec, makes it attractive for fixed wireless access and small cell backhaul applications. On-chip transmit-receive switching allows the antenna array to be shared. With an area of 9.6mm2, the chip is targeted at a 28nm CMOS process. Power consumption is said to be 231mW in receive and 508mW in transmit mode.

Key word：

5G,imec

Release time：2017-09-07 00:00 reading：1077 Continue reading>>

<span style='color:red'>Imec</span> Aims 2-D FETs at Sub-5-nm Node

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Imec Aims 2-D FETs at Sub-5-nm Node

　　Designers can extend Moore's Law scaling beyond the 5-nanometer node by choosing two-dimensional anisotropic (faster with the grain) materials such as monolayers of black phosphorus, according to Imec (Leuven, Belgium). Researchers from the nonprofit semiconductor research institute described their findings at the annual Imec Technology Forum, held in San Francisco on the eve of Semicon West (July 11-13).　　Imec’s demonstration project focused on field-effect transistors for high-performance logic applications as part of its Core CMOS program. Using co-optimization at the material, device, and circuit levels, Imec and its collaborators proved the concept using 2-D monolayers of anisotropic black phosphorus with a smaller effective mass in the transport direction. The black phosphorus was sandwiched between interfacial layers of low-k dielectric, with stacked dual gates deployed atop high-k dielectrics to control the atomically thin channels.　　Imec demonstrated the co-optimization approach at the 10-nm node but says the architecture could function with sub-half volt (<0.5-V) power supplies and an effective oxide thickness of less than 50 angstroms (0.5 nm), allowing its FETs to extend Moore’s Law for high-performance logic applications below the 5-nanometer node.　　The researchers predict the demonstrated architecture, materials, and co-optimization technique will yield reliable FETs with thicknesses all the way down to the single-atom level and gate lengths as short as 20 ?, advancing the nanowire FET as the successor to the FinFET. Imec is evaluating other materials besides black phosphor as prime candidates for extending nanowire FETs to atomic-level 2-D channels.　　Beyond extending Moore’s Law scaling laws for FETs, the 2-D materials will enhance the development of photonics, optoelectronics, biosensing, energy storage, and photovoltaics, according to Imec.　　The institute conducted the research in collaboration with scientists from Belgium’s Catholic University of Leuven (Belgium) and Italy’s Pisa University. Funding for the 10-nm demonstration came from the European Union’s Graphene Flagship research initiative along with Imec’s Core CMOS Program partners, which include GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, and TSMC.　　For more details, see the free Nature scientific report “Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes,” in which Imec presents guidelines on choosing materials, designing the devices, and optimizing the performance of sub-10-nm high-performance logic chips. Imec explains that at gate lengths below 5 nm, the 2-D electrostatistics associated with gate stacking become more of a challenge than direct source-to-drain tunneling for 2-D-material-based FETs.

Key word：

Imec,2-D FETs, Sub-5-nm

Release time：2017-07-14 00:00 reading：1168 Continue reading>>

model	brand	Quote
CDZVT2R20B	ROHM Semiconductor
MC33074DR2G	onsemi
RB751G-40T2R	ROHM Semiconductor
TL431ACLPR	Texas Instruments
BD71847AMWV-E2	ROHM Semiconductor

model	brand	To snap up
STM32F429IGT6	STMicroelectronics
BU33JA2MNVX-CTL	ROHM Semiconductor
ESR03EZPJ151	ROHM Semiconductor
TPS63050YFFR	Texas Instruments
IPZ40N04S5L4R8ATMA1	Infineon Technologies
BP3621	ROHM Semiconductor

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