2018 IEEE <span style='color:red'>IEDM</span> to showcase breakthrough in semiconductor technology
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2018 IEEE IEDM to showcase breakthrough in semiconductor technology

The 64thannual IEEE International Electron Devices Meeting (IEDM), the world’s largest, most influential forum for technologists to unveil breakthroughs and new concepts in transistors and related micro/nanoelectronics devices, will be held December 1-5, 2018 at the Hilton San Francisco Union Square hotel. The late-news submission deadline is September 10.The IEDM’s tradition of spotlighting more leading work in more areas of the field continues, even as the conference evolves to support the interdisciplinary and continuing educational needs of the scientists, engineers and students whose efforts make possible the expansion of the worldwide electronics industry.“We live in a time when electronics technology touches more aspects of business and industry than ever before,” said Kirsten Moselund, IEDM 2018 Publicity Chair and Research Staff Member at IBM Research–Zurich. “No matter what their specialty is, attendees will come away from the conference with a deeper understanding of the challenges and opportunities before them.”“In terms of industrial applications, the evening panel session on EUV will give attendees the opportunity to explore and debate this emerging technology with the very people who are driving it forward,” said Rihito Kuroda, IEDM 2018 Publicity Vice Chair and Associate Professor at Tohoku University. “This is just one way in which the IEDM conference gives people insights into the technologies that will become mainstream in a few years.”Here are details of some of the talks and events that will take place at this year’s IEDM. The papers to be presented in the technical sessions will be chosen in late September and highlights from them will be forthcoming soon thereafter:Focus SessionsQuantum Computing – Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. We are still in early stages, facing fundamental questions such as: What is the best way to implement a quantum bit of information? How to connect them together? How to scale to larger systems without being overwhelmed by errors? This session brings together experts at the forefront of quantum computing research. Starting from an applications perspective, attendees will hear about different approaches to address fundamental questions at the device level; the progress achieved so far; and next steps.Application Requirements for Quantum Computing, John Preskill, CaltechMaterials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBMTowards Scalable Silicon Quantum Computing, Maud Vinet, CEA-LetiSilicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio UniversityQubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, IntelScalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South WalesMajorana Qubits, Leo Kouwenhoeven, MicrosoftFuture Technologies Towards Wireless Communications: 5G and Beyond– 5G technology will drastically reduce limitations on accessibility, bandwidth, performance, and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This focus session will set a big picture view and then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas are coming together to enable the 5G platform.Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, IntelRFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC BerkeleyGaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron DevicesHighly Integrated mm-Wave Transceivers for Communication Systems,Vadim Issakov, InfineonBAW Filters for 5G Bands, Robert Aigner, QorvoReconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, PurdueChallenges for Wide Bandgap Device Adoption in Power Electronics– Wide bandgap (WBG) power devices offer potential savings in both energy and cost. But converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics and even market models. Can SiC or GaN push beyond what silicon can possibly achieve? What are the big challenges researchers should answer over the next decade? A team of experts will interpret the landscape and discuss challenges to the widespread adoption of these technologies.GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya UniversitySiC MOSFET for Mainstream Adoption, Peter Friedrichs, InfineonGaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, TransphormThe Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABBBarriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-EHigh to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AISTEffects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research LaboratoryInterconnects to Enable Continued Technology Scaling –BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained.Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, Naeemi, Georgia TechMechanisms of Electromigration Damage in Cu Interconnects, K. Hu, IBMInterconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, ImecMicrostructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT AustinIntegrating Graphene into Future Generations of BEOL Interconnects,-S. Philip Wong, StanfordInterconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials
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Release time：2018-08-20 00:00 reading：993 Continue reading>>
Intel, G’foundries Bring 10, 7nm to <span style='color:red'>IEDM</span>
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Intel, G’foundries Bring 10, 7nm to IEDM

　　Intel and Globalfoundries will describe their 10nm and 7nm process nodes, respectively at the International Electron Devices Meeting (IEDM) in December. The event also will host papers pointing to new directions in memories, medical and flexible electronics and transistors beyond today’s FinFETs.　　Intel will discuss several aspects of its 10nm node first unveiled in March. It sports FinFETs with a 7nm fin width at a 34nm pitch and a 46nm fin height made using self-aligned quadruple patterning. A 204 Mbit SRAM made in the process packs separate high-density, low voltage and high-performance cells that measure from 0.0312?m2 to 0.0441?m2.　　The 12-metal interconnect layers in the node can support multiple threshold voltages. Compared to its 14nm process, the 10nm node sports NMOS and PMOS current that is 71 percent and 35 percent greater. Cobalt wires in the lowest two metal layers offer up to 10x improvement in electro-migration and a 2x reduction in via resistance.　　For its part, Globalfoundries will detail a 0.0269?m2 SRAM cell made in its 7nm FinFET process tat was discussed at a September company event. Compared to its current 14nm process licensed from Samsung, the 7nm node should deliver 2.8x better routed logic density and more than 40 percent more performance or 55 percent lower power.　　Like Intel, the Globalfoundries node will support a range of threshold voltages. It uses self-aligned quad patterning to make fins and double patterning for metallization.　　A handful of papers will provide a view of research on the possible successors to the FinFET as a basic electronics switch.　　Imec researchers will present at least three papers on the subject, including oneon what it claims is the first circuit built with stacked silicon nanowires. The working ring oscillator used a new metallization process for n-type devices that led to greater control of threshold voltage.　　The MOSFET structures essentially wrap a gate around a nanowire to act as a transistor channel. In a separate paper, Imec will report performance characteristics of nanowires and nanosheets, arrays of the gate-all-around nanowires. Vertical test devices built in InGaAs showed Ion performance of 397?A/?m and peak transconductance of 1.6S/?m at Vds=0.5V.　　Separately, Globalfoundries will describe a ring oscillator built with 14nm ferroelectric FinFETs. It ran at the same frequencies but lower power than similar devices in silicon. The doped hafnia structures have negative capacitance, so they could be used in commercial fabs, it said.　　In memory papers, Macronix will report an advance in 3D NAND and SK Hynix will share work on ReRAM. In addition, IBM and CEA-Leti will give separate talks on their work in monolithic 3D integration.　　In heath care, Swiss researchers will describe a low power sensor made using FD-SOI that can collect and measure in real time biomarkers from sweat. Separately, a team led by the Houston Methodist Research Institute will describe implantable devices enabling controlled release over time of drugs or hormones via nanofluidic channels.　　Pointing to new directions in flexible electronics, researchers from the University of Texas at Austin will discuss how they built a variety of two- and three-terminal graphene and MoS2 devices on paper. The graphene devices achieved a record 25 GHz cutoff frequency and performance remained high even when the paper was rolled into a two-inch diameter roll.
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Release time：2017-10-19 00:00 reading：1139 Continue reading>>

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