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NVIDIA Enters PC Market with RTX Spark Featuring MediaTek-Co-Designed N1X CPU on TSMC 3nm

　　As traditional CPU leaders such as Intel push further into the AI accelerator market, NVIDIA is moving in the opposite direction—leveraging its dominance in AI computing to expand into the PC processor arena. At GTC Taipei on June 1, CEO Jensen Huang unveiled the NVIDIA RTX Spark, developed in partnership with Microsoft and powered by the new Arm-based N1X processor co-designed with MediaTek, according to NVIDIA and CNBC.　　According to CNBC, the initial rollout will include more than 30 notebook models and 10 desktop systems. RTX Spark-powered devices from Microsoft, Dell, HP, ASUS, Lenovo, and MSI are expected to debut this fall, marking NVIDIA’s first large-scale push into the Windows PC CPU market.　　CNBC adds that the platform combines NVIDIA’s Blackwell GPU architecture with the N1X CPU and 128GB of unified memory, bringing data center-class AI capabilities to personal computers. Notably, the new PC processor will be manufactured using TSMC’s 3nm process, which is currently produced exclusively in Taiwan, according to CNBC.　　More Spec Details　　Interestingly, as noted by The Verge, the flagship RTX Spark mirrors the DGX Spark almost exactly — 20 CPU cores, 6,144 GPU cores, 128GB of LPDDR5X memory — though NVIDIA plans to release leaner, more affordable variants, with some configurations dropping to just 16GB of RAM.　　Meanwhile, NVIDIA has provided additional details on the platform’s performance. According to The Verge, with up to 128GB of unified memory—on par with AMD’s previous-generation Strix Halo—RTX Spark laptops and desktops are also capable of hosting AI agents with up to 120 billion parameters, a capability Microsoft appears eager to integrate into Windows.　　Powered by RTX Spark, NVIDIA claims the system can render a 90GB 3D scene, edit 12K video, or run graphically intensive titles like Indiana Jones and the Great Circle at a smooth 100fps in 1440p—all within a 14mm-thin laptop operating without being plugged into power, the report adds.　　CNBC, citing an NVIDIA spokesperson, reports that RTX Spark is described as being “roughly equivalent” to the company’s flagship RTX 5070 laptop GPU.　　NVIDIA is certainly not the only player eyeing to expand its CPU footprint. As noted by CNBC, Apple now designs its own Arm-based processors for Mac computers, having rolled out a higher-end MacBook lineup powered by its latest M5 chips in March. In the same month, Arm unveiled its first in-house CPU, with Meta reportedly serving as the launch customer for the Arm AGI CPU, according to TechCrunch.

Key word：

NVIDIA

Release time：2026-06-02 10:29 reading：194 Continue reading>>

Trade news

Nexperia China Says MOSFET, Logic IC Supply Chains Complete as Independent Operations Largely in Place

　　After last year’s control dispute between Wingtech and Nexperia’s Netherlands headquarters sent shockwaves through the industry, Nexperia China now says it has made significant progress in building independent operations. According to EE Times China, Wingtech Chairwoman Ruby Yang announced on May 29 that Nexperia China has largely completed the setup of its independent operating system.　　Yang revealed that Nexperia China’s core management, R&D, and market teams are now fully based in China. The report notes that the company’s capacity and delivery capabilities have steadily recovered, while it continues to build a “China for China, China for Global” full-stack supply chain across wafer manufacturing, packaging and testing, and quality control.　　The announcement comes as Wingtech faces mounting pressure. According to ESM China, the company said on April 29 that its auditor issued a “disclaimer of opinion” on its 2025 financial report, triggering a delisting risk warning under relevant rules.　　Full-Stack Supply Chains Advance Across Key Product Lines　　In terms of product layout, Nexperia China currently covers three core business lines: MOSFETs, logic ICs, and bipolar transistors, including protection devices. Yang said none of the three previously had a fully domestic, full-stack supply chain. However, according to the report, MOSFET and logic IC products have now established such supply chains.　　The bipolar transistor line is being upgraded to a 12-inch platform and is expected to complete its full-stack domestic supply chain within 2026. Bipolar transistors entered small-batch mass production in March 2026, with capacity for protection devices such as ESD (Electrostatic Discharge) and TVS (Transient Voltage Suppressor) products expected to gradually come online in the second half of 2026, the report notes.　　Under the plan, 19 products are expected to be ready for supply by next month, covering more than 80% of demand, the report adds. Despite the severe supply-chain fallout from last year’s Wingtech-Nexperia control dispute, the report indicates that Nexperia China has maintained large-scale delivery capabilities. Since mid-October 2025, it has shipped more than 11 billion chips to over 800 customers.　　Wingtech Seeks Court Action in Nexperia Control Dispute　　Meanwhile, the battle for control of Nexperia has escalated further. According to South China Morning Post, Wingtech said last week that it had filed a lawsuit in a court in China’s southern Guangdong province against Nexperia and three of its executives. The suit demands the restoration of full corporate control and 8 billion yuan, or US$1.18 billion, in compensation.　　As Bloomberg notes, Wingtech asked the court to order the defendants to stop carrying out or supporting the disputed measures, including by withdrawing legal proceedings in the Netherlands and revoking a Dutch ministerial order issued last September under the Goods Availability Act. If the defendants fail to comply, Wingtech would seek the transfer of Nexperia and related subsidiaries to the company free of charge.

Key word：

Nexperia China

Release time：2026-06-02 10:25 reading：193 Continue reading>>

Trade news

Japan–U.S. NAND Alliance Steps Up Investment as Kioxia–SanDisk Capex Reportedly Rises 40% YoY

　　As South Korea’s memory giants shift focus toward 1c DRAM capacity expansion amid surging demand, Global Economic, citing German tech outlet ComputerBase, reports that the Kioxia–SanDisk alliance is moving fast to reassert its position in the NAND market, capitalizing on an investment gap as Samsung Electronics and SK hynix divert resources toward HBM.　　According to the reports, the U.S.–Japan NAND consortium is expected to execute total capital expenditure of $4.5 billion (about KRW 6.75 trillion) in the current fiscal year, marking a 41% year-on-year increase.　　Notably, a key focus of the alliance would likely be the 10th-generation NAND. Nikkei previously reported that Kioxia plans to begin mass production at its Kitakami site in Iwate Prefecture in 2026. However, given the jump to a 332-layer architecture—up from 218 layers in its 8th-generation devices—the company is expected to repurpose its newly operational Kitakami K2 facility, which began production in September, to support output, according to Nikkei.　　ComputerBase, cited by Global Economic, attributes the strong NAND demand supporting Kioxia–SanDisk’s investment to a structural shift in AI workloads: As AI moves from the training-heavy infrastructure build-out phase to large-scale inference deployment, demand is rising for high-performance, ultra-high-capacity storage.　　At the same time, storage is accounting for a growing share of hyperscaler data center capex, while SSD capacity per GPU is more than doubling year over year, the report notes. As a result, next-gen AI servers are increasingly being designed with tens of terabytes of storage per GPU, driving a sustained surge in NAND demand, the report adds.　　Fewer Layers, Comparable Density　　ZDNet also reports that in its recent earnings briefing, Kioxia identified the launch of 10th-generation BiCS NAND as a key priority for fiscal 2026 (April 2026–March 2027). The report adds that the company applies its proprietary BiCS (Bit Cost Scalable) architecture to its scaling roadmap, with the 10th-generation device delivering 59% higher storage density per unit area and a 33% improvement in data transfer speed compared with the 218-layer generation.　　According to ComputerBase, Kioxia’s stacking approach enables comparable density with fewer layers, translating into meaningful cost advantages. A lower stack height also simplifies vertical etching, reduces high-cost equipment runtime, and helps mitigate wafer warpage defects.　　Based on 3D NAND density estimates cited by Global Economic from ComputerBase, Kioxia / SanDisk BiCS10 is projected to reach 37.6Gb per square millimeter in QLC configuration, which would surpass Samsung Electronics’ upcoming 430-layer V10 TLC architecture at around 28.0Gb.　　Samsung, SK hynix Hold Back　　However, TrendForce indicates that major NAND Flash suppliers will add virtually no new production capacity in 2026, and it seems that South Korean memory players are taking a different approach with Kioxia and SanDisk.　　As highlighted by Global Economic, Samsung Electronics and SK hynix have both adjusted their 10th-generation NAND ramp-up schedules: Samsung has reportedly pushed back its V10 production timeline from the second half of 2025 to 2026, while SK hynix is targeting early 2027 for full-scale production.　　ZDNet also reports that Samsung Electronics had initially planned to begin mass production of its 430-layer 10th-generation NAND this year, but the timeline has been delayed to at least 2027, citing technical complexity and softer demand conditions. The report adds that Samsung is still reviewing investment timing, with no concrete equipment orders confirmed, and that SK hynix faces a similar situation.　　Global Economic notes that if the U.S.–Japan NAND alliance succeeds in lowering cost per terabyte and accelerating QLC enterprise SSD adoption, demand could shift more rapidly toward AI data center storage. Even so, Samsung and SK hynix remain competitive, supported by stable 9th-generation yields and strong enterprise SSD customer bases, the report adds.

Key word：

Kioxia

Release time：2026-06-01 10:45 reading：194 Continue reading>>

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Samsung Starts Shipping Industry-First HBM4E Samples 3 Months After HBM4 Ramp; Performance Up 20%+

　　Just months after rolling out HBM4 shipments in early 2026, Samsung has begun providing samples of the industry’s first 12-layer HBM4E to major global partners, according to the company’s latest press release.　　Given that HBM4 shares the same 1c DRAM process and 4nm base die architecture as HBM4E, and is already in mass production, industry observers suggest the newly shipped HBM4E samples are also well positioned to transition into mass production. Samsung adds that it plans to proceed with HBM4E mass production in line with client-specific timelines.　　Meanwhile, Samsung is also expanding mass production and supply of HBM4, which became the world’s first HBM4 to enter mass production and shipment in February. In December last year, Samsung’s HBM4 received top-tier evaluation after demonstrating an industry-leading 11.7Gbps speed in System-in-Package (SiP) testing, the final certification stage, the company adds.　　According to News1, the latest development makes Samsung the first to supply HBM4E. Industry observers cited by the report also noted that starting from HBM4, customer-specific design flexibility and stable large-scale supply capabilities will become even more critical. Against this backdrop, Samsung’s integrated strengths across memory, foundry, and advanced packaging are expected to stand out even more clearly, the report adds.　　HBM4E Upgrade with 20% Performance Boost, 30% Higher Capacity　　In terms of performance, Samsung notes that HBM4E marks a notable upgrade over the previous generation, offering a stable 14Gbps pin speed that can scale up to 16Gbps for more demanding AI workloads. Compared with HBM4, the new memory delivers over 20% higher performance and reaches bandwidth of up to 3.6TB/s per stack, significantly improving compute efficiency for large language models (LLMs) and next-generation AI systems.　　Additionally, Samsung’s 12-layer HBM4E is currently offered in a 48GB capacity, which is more than 30% higher than the previous generation. The company plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) variants to better align with diverse customer requirements as well.　　From an efficiency standpoint, Samsung highlights that advanced low-power design techniques and an optimized packaging architecture have improved energy efficiency by 16% while reducing thermal resistance by more than 14% compared with the previous generation.　　HBM4E Progress Among Rivals　　Meanwhile, progress from SK hynix and Micron in HBM4E has come under closer market scrutiny following Samsung’s advances. According to Yonhap News Agency, SK hynix had initially planned to begin HBM4E sample shipments in the second half of this year, but recent reports indicate smoother-than-expected development progress, bringing forward its timeline.　　On the other hand, Micron said its first HBM4E product will follow JEDEC standards, with mass production ramp-up targeted for 2027, according to STOCK Analysis.

Key word：

Samsung

Release time：2026-05-29 10:18 reading：335 Continue reading>>

Trade news

Micron More Upbeat on Outlook, Reportedly Sets 2027 HBM4E Ramp with TSMC for Standard, Custom Logic Dies

　　Two months after its March earnings call, Micron is turning more upbeat on its outlook, while providing additional details on its custom HBM development progress. At the J.P. Morgan 54th Annual Global Technology, Media and Communications Conference, Micron’s Global Operations EVP Manish Bhatia, via STOCK Analysis transcript, said the company’s first HBM4E will be a JEDEC-standard product, with ramp-up scheduled for 2027.　　While Micron is still using 1-beta DRAM for HBM4, Bhatia said the company is expected to transition to 1-gamma DRAM in the HBM4E era. He also confirmed that the logic dies for both standard and custom HBM4E are expected to be manufactured by TSMC.　　When asked about the margin profile of customized products, Bhatia, according to STOCK Analysis, highlighted that value creation stems from multiple proprietary layers: design innovation, robust core DRAM development, and advanced packaging.　　He emphasized that customization represents the next evolution of this value expansion, and as the value increases, customers are expected to be willing to pay for the added customization.　　Improving Outlook vs. Previous Earnings Call　　According to Bhatia, Micron now expects tight conditions across HBM, DRAM, and NAND to persist well beyond 2026. Thus, he noted that the financial outlook has strengthened since the company’s last earnings call, and it is on track for another substantial record free cash flow in fiscal Q3.　　Notably, Bhatia pointed out that while pricing has largely played out as expected, demand remains very strong. He added that the AI ecosystem is shifting from human interactions to agentic and even machine-to-machine workflows, with these agentic workloads increasingly driving inference demand. As inference takes up a larger share of workloads, memory is increasingly seen as a strategic asset for customers, he said.　　Against this backdrop, Micron said in March that it had secured its first strategic customer agreement—a five-year deal with a large customer. Since then, the company has made meaningful progress on additional SCAs, with other customers also showing strong interest in establishing similar strategic relationships with Micron, including in NAND, Bhatia said.　　India Capacity Reported Booked up　　Amid tight demand, Bhatia also said Micron’s global expansion is accelerating. He noted that its Idaho 1 site is progressing well, with the company pulling forward its wafer output timeline from the second half of 2027 to mid-2027.　　Surging memory demand is also driving ramp-up at Micron’s new semiconductor assembly and test facility in Sanand, Gujarat, which began operations in late February. In a separate report by Business Standard, Micron’s entire memory production capacity in India has been fully booked amid strong demand.　　According to a previous Business Standard report, at full capacity, the facility could account for up to 10% of Micron’s global output, supplying both domestic and international markets.　　Sumit Sadana, executive vice-president and chief business officer at Micron, reportedly told Indian media outlet The Economic Times that the global semiconductor memory shortage triggered by the AI boom is proving far more severe than many companies currently anticipate, with the crunch potentially extending well beyond 2028 despite aggressive capacity expansion across the industry.

Key word：

Micron

Release time：2026-05-25 10:44 reading：421 Continue reading>>

Trade news

Intel 18A Yields Up 7%–8% Monthly as 2H26 Customers Expected; Said to Push 18A CPUs Amid Shortages

　　Intel’s turnaround appears to be gaining momentum. According to CNBC, Intel CEO Lip-Bu Tan said the company’s foundry business is making progress, with 18A process yields now improving by 7% to 8% per month, signaling advancement from earlier challenges.　　More significantly, Tan said the improvements are beginning to attract customer interest, with Intel expecting commitments from multiple foundry customers in the second half of 2026, the report highlights. The remarks align with earlier comments from CFO David Zinsner, who said signals from external foundry customers would become “more concrete” in the second half of the year and into early 2027.　　Intel Reportedly Pushes 18A CPUs Amid Supply Tightness　　Recent CPU shortages have also brought renewed attention to Intel, which is reportedly promoting processors built on its 18A technology. According to Nikkei, sources say Intel is encouraging key PC partners across the U.S., China, and Taiwan to increase adoption of CPUs produced using the process, which only became available late last year.　　Sources add that the company has prioritized supply of chips based on its older Intel 7 process for server and industrial applications. Intel’s push to promote its most advanced chips comes as it seeks to capitalize on the AI race and regain leadership in advanced chipmaking, the report adds.　　14A Seen as Intel’s Next Push Against TSMC　　Beyond 18A, according to CNBC, Tan said Intel’s next-generation 14A process could eventually compete with TSMC, adding that it is expected to arrive around the same time as TSMC’s comparable technology — a development he described as a “major, major breakthrough.” As noted by Wccftech, Tan said Intel expects risk production for its 14A technology in 2028, followed by volume production in 2029, placing its timeline alongside TSMC’s. He added that multiple customers are already engaging with Intel as the company has made its 0.5 PDK available.　　EMIB Shows Early Customer Commitment as Substrate Prepayments Emerge　　Another major technology highlighted by Lip-Bu Tan is EMIB, which he described as one of the most advanced chip packaging technologies. According to Wccftech, Tan said customer commitment has become evident, with some customers even prepaying for substrates to secure supply amid ongoing shortages.　　Wccftech notes that EMIB was recently said to have reached 90% yields. By contrast, Commercial Times notes that TSMC’s CoWoS currently mass-produced 5.5-reticle-size version — the world’s largest today — has already achieved yields of 98%.

Key word：

Intel

Release time：2026-05-20 11:32 reading：557 Continue reading>>

Trade news

NVIDIA Reportedly Plans GPU-Direct Storage for Vera Rubin, Raising Expectations for HBF Beyond HBM

　　As AI models continue to scale, HBM may struggle to meet future memory-capacity demands, prompting industry experts to view GPU-driven storage architectures as a potential next frontier. According to The Elec, NVIDIA and Amazon are reportedly advancing storage architectures that allow GPUs to directly control storage devices such as SSDs. NVIDIA is said to plan the introduction of GPU-Initiated Direct Storage Access (GIDS) starting with its Vera Rubin AI platform, a shift that could accelerate the emergence of high-bandwidth flash (HBF), the report notes.　　Citing Song Ki-hwan, a professor in the Department of System Semiconductor Engineering at Yonsei University, the report explains that GIDS goes beyond existing GPU Direct Storage (GDS) architecture. Under GDS, CPUs issue data requests to storage devices before data is transferred to GPUs. GIDS advances this by allowing GPUs to access storage directly, bypassing CPUs and DRAM.　　Both GIDS and GDS aim to overcome data-transfer bottlenecks tied to traditional von Neumann computing architectures. Microsoft and AMD are also said to be exploring similar approaches. The report, citing Song, adds that traditional data-transfer methods are inefficient because CPUs are structurally limited in thread processing, while GPUs can generate tens of thousands of parallel threads. Song also notes that GPU-HBM data transfer already accounts for roughly half of total system power, strengthening the case for HBF architectures that place ultra-fast NAND closer to GPUs to address future AI bottlenecks.　　GIDS Could Accelerate HBF and Expand NAND’s Role in AI Memory　　The emergence of GIDS could allow NAND storage to take on a larger role in AI memory systems while easing pressure on HBM capacity. As the report notes, this shift would require higher-performance NAND flash capable of keeping pace with GPU processing speeds. One proposed approach is high-bandwidth flash (HBF), which stacks NAND flash vertically in a structure similar to HBM and connects it using through-silicon vias (TSVs).　　The report notes that NAND flash offers roughly 30 times higher bit density than DRAM, enabling far greater memory capacity in a similar footprint. According to Song, combining six HBF units with two HBM units could increase GPU memory capacity more than 16 times, from 192GB to 3,120GB, potentially supporting AI models with parameter sizes around 16 times larger than current architectures.　　Still, NAND flash has endurance limits, typically supporting only around 100,000 write-and-erase cycles versus DRAM’s near-unlimited write capability. As a result, HBF is seen as better suited for storing AI model parameters, which remain largely unchanged during inference and function as read-only workloads.　　Meanwhile, memory makers have also been exploring GPU-driven memory architectures. According to an Edaily report last year, sources said Samsung Electronics is actively researching next-generation high-performance Z-NAND. The company is also developing GIDS technology that would allow GPUs to directly access Z-NAND-based storage devices. If implemented, GPUs would be able to access Z-NAND devices without intermediaries, potentially shortening processing times for AI workloads.

Key word：

NVIDIA

Release time：2026-05-20 11:20 reading：803 Continue reading>>

Trade news

First Intel Wildcat Lake Laptops Near Launch; Reportedly Built on 18A, Taking Aim at Apple’s MacBook Neo

　　The first laptops powered by Intel’s “Wildcat Lake” Core Series 300 processors for the entry-level PC segment are reportedly nearing launch. According to Wccftech, Intel Core Series 3 laptops could hit retail shelves as early as next week, with initial models including 14-inch and 16-inch designs from Honor and ASUS, while more OEMs are expected to follow.　　Chinese media outlet Mydrivers notes that the Honor Notebook X14 2026 Combat Edition will be the first commercially available laptop based on Intel’s Wildcat Lake platform, featuring an Intel Core 5 320 processor. Another Wccftech report notes that the device comes with 16GB of LPDDR5X 7467 MT/s memory, double the capacity of Apple’s MacBook Neo, along with a 512GB SSD. By comparison, the Neo starts at 256GB of storage and tops out at 512GB.　　Intel’s Wildcat Lake Targets AI PCs With Better Battery Life　　The SoC package integrates two dies, with the primary die built on Intel’s 18A node, according to TechPowerUp. This die features a 6-core CPU configuration, NPU 5 delivering 40 TOPS of INT8 performance, and a GPU with up to two Xe3 cores. It also integrates the memory controller and cache pool. Meanwhile, Intel dedicates the second die to I/O functions, the report adds.　　Wccftech notes that Intel’s Core Series 3 emphasizes AI capability and battery efficiency, marking the company’s first hybrid AI-ready Core Series processor. The report adds that the chips are designed for all-day battery life and everyday productivity, offering up to 2.1 times faster creation and productivity performance, up to 64% lower processor power consumption, and up to 2.7 times higher AI GPU performance compared with previous-generation Intel Core 7 150U processors.　　Looking ahead, Wildcat Lake could see broader adoption across future devices. TechPowerUp reports that Google is likely to pair its rumored “Googlebook” laptops with Intel’s latest Core Series 300 “Wildcat Lake” processors. However, Intel is not expected to be the exclusive platform provider, with Qualcomm and MediaTek also said to be among Google’s partners.

Key word：

Intel Wildcat Lake

Release time：2026-05-19 10:42 reading：609 Continue reading>>

Trade news

YC Chem Reportedly First to Supply Glass Substrate Photoresists; Customer Eyes Year-End Mass Production

　　South Korea’s YC Chem has reportedly become the first in the industry to supply photoresists for glass substrates. According to The Elec, sources say the company is supplying i-line photoresist, stripper, and developer materials for glass substrates to a customer after receiving a purchase order (PO) following qualification tests.　　As supply of related materials begins to ramp up, commercialization of glass substrates also appears to be drawing closer, the report notes. Current shipments are intended for the customer’s prototype production, with material supply volumes expected to increase gradually as the customer moves toward mass production from the end of this year.　　The company is also seeking additional customers. According to the report, it is currently in discussions with more than three companies regarding the supply of glass substrate materials. With some firms, sample testing is underway for negative photoresists and glass substrate coating materials.　　YC Chem has also supplied prototype coating materials for glass substrates to customers. These materials are intended to minimize cracking and warpage caused by differences in thermal expansion coefficients (CTE) and thermal conductivity between glass and copper. According to the report, the products are currently undergoing qualification testing.　　The report notes that the coating materials are used in embedding-type glass substrates, which integrate circuits and passive components directly within the glass substrate itself.　　Key Requirements for Photoresists in Glass Substrate Manufacturing　　As the report points out, the glass substrate photoresist supplied by YC Chem is based on i-line technology, which uses a 365-nanometer (nm) mercury lamp wavelength in the lithography process. Notably, the report points out that, unlike extreme ultraviolet (EUV) photoresists used in advanced semiconductor manufacturing, glass substrate production places greater emphasis on thicker film thickness and strong etch resistance.　　In particular, the report states that through-glass via (TGV) processes require strong chemical durability and high etch resistance during hole formation and copper plating. As a result, demand is increasing for longer-wavelength lithography materials such as i-line and krypton fluoride (KrF)-based photoresists.　　In South Korea, Samyang NC Chem is also developing photoresist materials for glass substrates. The report adds that the company has supplied samples to more than two customers and is reportedly aiming for mass production next year.　　As major companies accelerate glass substrate development, securing stable material supplies is becoming increasingly important. A January Chosun Biz report said Absolics is diversifying suppliers by adding a domestic partner for glass substrate photoresists, reducing reliance on Japan’s TOK, while also reviewing process dualization for TGV and plating processes through additional collaborators.

Key word：

YC Chem

Release time：2026-05-18 13:05 reading：612 Continue reading>>

Trade news

Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%

　　Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.　　The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.　　More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.　　The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.　　Commercialization Timeline Remains Unclear　　Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.　　Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.　　SK hynix Advances Mobile AI Packaging　　SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.　　Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.

Key word：

Samsung

Release time：2026-05-15 10:49 reading：694 Continue reading>>

model	brand	Quote
BD71847AMWV-E2	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
MC33074DR2G	onsemi
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor

model	brand	To snap up
TPS63050YFFR	Texas Instruments
STM32F429IGT6	STMicroelectronics
IPZ40N04S5L4R8ATMA1	Infineon Technologies
BU33JA2MNVX-CTL	ROHM Semiconductor
ESR03EZPJ151	ROHM Semiconductor
BP3621	ROHM Semiconductor

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