Imec and ASML announce <span style='color:red'>EUV</span> lithography collaboration
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Imec and ASML announce EUV lithography collaboration

imec, the research and innovation hub in nanoelectronics and digital technologies, and ASML, a leading developer of lithographic equipment, have announced the next step in their ongoing and extensive collaboration.The two are looking to accelerate the adoption of EUV lithography for high-volume production, including the current latest available equipment for EUV (0.33 Numerical Aperture, NA). Moreover, they are looking to explore the potential of the next-generation high-NA EUV lithography to enable printing of even smaller nanoscale devices advancing semiconductor scaling towards the post 3 nanometer Logic node. As a result they have established a joint high-NA EUV research lab.In 2014, they created a joint research centre, the Advanced Patterning Center, to optimize lithography technology for advanced CMOS integration and to prepare the ecosystem to support advance patterning requirements. The next stage of this co-operation will see the installation of ASML’s most advanced and high-volume production dedicated EUV scanner (NXE:3400B) in imec’s cleanroom.Using imec’s infrastructure and advanced technology platforms, researchers and partner companies will be able to pro-actively analyse and solve technical challenges such as defects, reliability and yield, and as such help to accelerate the EUV technology’s industrialisation.With a 250W light source, ASML’s newest EUV system throughput will be more than 125 wafers per hour, one of the industry’s most important requirements for high-volume production. The NXE:3400B will also be equipped with the latest alignment and leveling sensors, to enable optimal process control at this high throughput. This will facilitate the overlay matching of the NXE:3400B to that of the latest immersion scanner, NXT:2000i, that will also be installed in imec’s cleanroom in 2019. In addition, ASML and imec will expand the metrology capability with new ASML YieldStar optical metrology and ASML-HMI Multi-electron beam metrology equipment, allowing more accurate and faster evaluation of nanoscale structures.The joint high-NA EUV research lab will see researchers from both organisations experiment with the next generation of EUV lithography at higher NA. Systems with a higher NA project the EUV light onto the wafer under larger angles, improving resolution, and enabling printing of smaller features. More specifically, the new high-NA EUV system, EXE:5000, that will be installed in the joint research lab, will have an NA of 0.55 instead of 0.33 in current NXE:3400 EUV systems.Already, the first joint scientific projects to facilitate the introduction of high-NA EUV, are ongoing. In the joint research lab, ASML and imec will perform research on the manufacturing of the most advanced nanoscale devices by high-NA EUV and assist the ecosystem of equipment and material suppliers to prepare for the introduction of high-NA EUV technology to the industry.Commenting Luc Van den hove, President and CEO of imec, said: “The new EUV scanners and ASML metrology equipment will allow our industry partners to perform collaborative research on the most advanced and industry relevant lithography and metrology equipment. ASML and imec have a nearly 30 year long tradition of joint research, leading to breakthrough patterning research to advance the semiconductor industry roadmap.”
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Release time：2018-10-26 00:00 reading：1340 Continue reading>>
Samsung Ramps 7nm <span style='color:red'>EUV</span> Chips
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Samsung Ramps 7nm EUV Chips

The race is on to get the first chip made with extreme ultraviolet lithography out the foundry door.Samsung said it has taped out and is ramping multiple 7nm chips using EUV following a similar announcement earlier this month from its larger foundry rival TSMC. Samsung also gave its supporting IP and EDA infrastructure a boost and detailed its packaging capabilities in an effort to catch up with TSMCs ecosystem.The South Korean giant also announced it is sampling 256-GByte RDIMMs based on its 16-Gbit DRAM chips and plans for solid-state drives with embedded Xilinx FPGAs. But the 7nm news was the highlight of the event, a milestone fueled in part by its internal development of an EUV mask inspection system.The 7LPP process will deliver up to a 40% shrink and up to 20% higher speeds or 50% lower power consumption compared to its 10nm node. Separately, Samsung said it now has 50 foundry partners including Ansys, Arm, Cadence (which has digital and analog flows for 7nm), Mentor, Synopsys and VeriSilicon, which said it taped out a chip in the 7nm process.The process is said to have attracted customers who include Web giants, networking companies and mobile vendors such as Qualcomm. However, Samsung expects no customer announcements until early next year.EUV systems supported 250W light sources on a sustained basis since early this year at Samsung’s S3 fab in Hwaseong, South Korea, said Bob Stear, director of foundry marketing at Samsung. The power level drove throughput up to the needed 1,500 wafers/day for production. Since then, EUV systems have hit a peak 280W, and Samsung targets 300W, he said.EUV eliminates a fifth of masks required with traditional argon-flouride systems, raising yields. However, the node still requires some multi-patterning in base layers at the front-end-of-line, said Stear.Samsung developed its own system to compare and fix expected and actual mask patterns to speed EUV into production. G. Dan Hutcheson of VLSI Research described it as a mask review system because it’s unclear if it is as automated as typical third-party inspection systems.The 7nm node will meet Grade 1 AEC-Q100 automotive standards by the end of the year. In packaging, Samsung is developing an RDL interposer that will enable up to 8 HBM stacks on a single device. It is also working on a process to embed passives in a substrate to save space for data center chips.Both Samsung and TSMC will apply EUV probably only to two chip layers at 7nm, so far not using protective pellicles that are still in development, said Handel Jones, president of International Business Strategies. They will extend EUV to perhaps six layers at 5nm nodes, but that may not come until 2021 when pellicles will have sufficient durability and light-transmission capabilities, he said.“Samsung is about six months ahead with an EUV process because they have been using the systems with DRAM and logic, but TSMC is way ahead in enablement with IP and tools and is working with more customers such as AMD, Apple, HiSilicon and Nvidia, among others,” said Jones.Another analyst said Cisco, a customer of the former IBM foundry business, is now working with TSMC for 7nm products. Qualcomm is expected to split its 7nm work between TSMC and Samsung.Nevertheless, Jones forecasts the South Korean giant’s revenues, on track to hit $90 billion this year, could leap to more than $150 billion by 2027. The prediction is based more on growth in its memory business, where he estimates Samsung will rise to command 50% of DRAM and 45% of NAND sales.Samsung is on track to start production of 5 and 4nm nodes before June, providing evolutionary improvements with the same device sets. PDKs for the nodes could be released before the end of the year, and a second shell for EUV production is being built next to the S3 fab, said Stear.The three nodes will move the contact closer to and eventually over the gate to increase density and reduce metal pitches. It’s an approach Intel previously discussed for its 10nm node that is still not in volume production.“We’re doing contact-over-gate in steps. It’s a hard problem to solve, as some are finding out,” said Stear.Samsung announced in May its plans to move to gate-all-around transistors also described as nanosheets for a 3nm node. It aims to drop nominal voltage to a new low to continue power savings. First cut of a version 0.1 PDK for a 3nm node could be available by June.Samsung has a laundry list of packaging options already available in house.In its core memory business, Samsung said it is sampling 256GByte RDIMMs made with its 16Gbit chips. The cards running at DDR4 speeds up to 3200 MHz and supporting 50ns reads and writes should be in production before the end of the year.The chips are made in a 1y-nm process first described a year ago. It was not clear whether EUV is being applied to the 1y process. However, follow-on 1z and 1a nodes will increasingly use EUV, Samsung’s head of DRAM development, Seong Jin Jang, suggested in a talk here.Samsung showed eight of the DIMMs running on an AMD Epyc server. They hit 3.2 million operations/second at 170W compared to its existing 128GB cards delivering 3.8 million ops/s at 225W.Ultimately, Samsung aims to boost DIMMs to 768 GBytes. It also aims to raise HBM data rates to 512 GB/second from 307 GB/s today. GDDR6 graphics memories will hit 22 Gbits/s from 18 Gbits/s today, and LPDDR memories will fall from 24 mW/GB to 12 mW/GB, he added without providing time frames.Separately, Samsung announced plans for smart solid-state-drives (SSDs) using embedded Xilinx Zynq FPGAs to bolster performance 2.8-3.3x. The devices target a wide range of database, AI, video and storage applications.The SSDs will provide an easier way to scale performance than matching banks of standard FPGAs to separate accelerators, the company said. The products, still in a prototype phase, will use a range of densities and medium-grade FPGAs.The smart SSD is so far only a prototype without specs or a delivery date 
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Release time：2018-10-18 00:00 reading：2020 Continue reading>>
Intel Ceding Leadership in <span style='color:red'>EUV</span>
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Intel Ceding Leadership in EUV

The few chipmakers that lead technology development are betting that by next year extreme ultraviolet lithography (EUV) will take transistor densities on semiconductors another step closer to their physical limits.Intel, once the world’s biggest chipmaker, appears to have given up efforts to lead the pack in EUV. The company was among the first to start EUV development in the late 1990s.Intel will not be inserting EUV anytime soon, according to Mark Li, an electronics engineer and analyst with Bernstein. The company is having difficulties ramping 10nm, and EUV in Intel’s 7nm, expected several years from now, remains an open question, he adds.In the meantime, Samsung and TSMC are pressing ahead with EUV, albeit cautiously. While Samsung and TSMC are developing EUV for introduction in 2019, the rest of the world’s major chipmakers appear to be falling behind.Intel, for now, appears to be a distant third in the race.“Intel has effectively lost its manufacturing leadership,” according to Mehdi Hosseini, an analyst with Susquehanna.Globalfoundries last year said it expects to use EUV tools in 2019 production flows to make contacts and cut masks.Samsung will introduce 7nm, the newest node, later than TSMC but with EUV, according to Li. While TSMC's enhanced version of 7nm, called 7nm+, will be slightly later with fewer EUV layers, the flexibility of having both EUV and non-EUV versions will be an advantage, he says.Samsung has consistently planned for EUV insertion with a minimum of 8-10 layers at 7nm compared with a few layers that TSMC has planned at 7nm+, according to Hosseini.Intel may be biding its time until the technology is more mature.The company told EE Times last year that it is committed to bringing EUV into production as soon as the technology is ready at an effective cost. Intel may not insert EUV into its process technology until late 2021, according to a forecast from Bernstein.“It now appears that Samsung's aggressive plans have backfired, and prospective customers are not so pleased with Samsung's 7nm process recipe” Hosseini said.Hosseini added that Susquehanna doesn't believe that Globalfoundries had gained much traction at 7nm. Globalfoundries subsequently announced that it suspended work on 7nm node, and will lay off nearly 5% of its workforce and make its ASIC group a wholly-owned subsidiary so it can partner with one of the remaining 7nm foundries.The chip industry’s cautious adoption of EUV lithography will probably not have an impact on TSMC’s business with Apple, according to Bernstein’s Li.“Though Apple may not be using EUV next year, we believe TSMC will retain Apple's exclusive processor business,” he said. “We also don't think this will negatively impact TSMC's EUV plan.”TSMC will be able to bring EUV to mass production in the second half of 2019 as many customers, including mobile, GPU and cryptocurrency miners, are interested in 7nm+, Li said.For now, TSMC leads its competitors with the rollout of 7nm technology, and that’s one of the key reasons the company has been able to increase business with Apple and other key customers, according to Susquehanna's Hosseini.“TSMC appears to be winning most of the leading-edge design wins due to better 7nm process technology performance, lower power consumption and better area density,” he told EE Times. “TSMC’s 7nm is expected to account for more than 20 percent of the company’s revenue in the December quarter as the customer mix includes more than 50 different product tapeouts for diverse applications including APs, GPUs, server CPUs, network processors and FPGAs.”Technology leadership should help TSMC diversify its customer base in the future.“TSMC will increasingly benefit from non-smartphone markets over time as new growth drivers start to inflect: 5G basestations, cloud computing, autonomous vehicles and AI are all nascent but important long-term opportunities in high-performance compute that require leading-edge technology,” according to Arete analyst Brett Simpson.
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Release time：2018-09-03 00:00 reading：1073 Continue reading>>
50 <span style='color:red'>EUV</span> Systems Set to be Shipped by ASML by 2019
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50 EUV Systems Set to be Shipped by ASML by 2019

Dutch semiconductor equipment vendor  ASML said Wednesday it is on track to ship 20 extreme ultraviolet (EUV) systems in 2018 and expects to ship at least 30 more in 2019.The company's estimates came as part of ASML's second quarter financial report, which included better-than-expected sales of EUV tools and overall sales of about $3.2 billion. "Gross margin was slightly above our guidance, reflecting the strength of our DUV and applications business and progress in EUV profitability," said ASML CEO Peter Wennink.ASML shipped four EUV systems in the second quarter, one more than forecast, as logic customers prepare to ramp next-generation devices starting later this year, Wennink said.EUV — the successor to the workhorse deep ultraviolet (DUV) technology in advanced semiconductor manufacturing — is finally on the cusp of production after years of delays. Leading-edge semiconductor manufacturers include Samsung, Intel and TSMC are planning to use EUV in volume production beginning in the next year, though concerns remain about the availability of the EUV power source and other items in the EUV supply chain, including pellicles.ASML says it has now demonstrated four-week availability of well above 85% on a number of its new NXE:3400B EUV systems and is executing several programs to improve consistent availability to over 90% in 2019.Wennink said ASML's deep-ultraviolet lithography business continues to thrive, driven largely by the memory market, which  continues to require a significant number of lithography systems at least throughout this year and into 2019. After an excellent first half of 2018, we expect the second half."After an excellent first half of 2018, we expect the second half to be stronger, with improved profitability and continued growth from Q3 to Q4,” Wennink said.For the third quarter,  ASML said it expects sales of between 2.7 billion and 2.8 billion euro (roughly $3.15 billion to $3.26 billion).
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Release time：2018-07-23 00:00 reading：1077 Continue reading>>
ASML to Ship 20 <span style='color:red'>EUV</span> Systems in 2018
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ASML to Ship 20 EUV Systems in 2018

Dutch semiconductor equipment vendor  ASML said Wednesday it is on track to ship 20 extreme ultraviolet (EUV) systems in 2018 and expects to ship at least 30 more in 2019.The company's estimates came as part of ASML's second quarter financial report, which included better-than-expected sales of EUV tools and overall sales of about $3.2 billion. "Gross margin was slightly above our guidance, reflecting the strength of our DUV and applications business and progress in EUV profitability," said ASML CEO Peter Wennink.ASML shipped four EUV systems in the second quarter, one more than forecast, as logic customers prepare to ramp next-generation devices starting later this year, Wennink said.EUV — the successor to the workhorse deep ultraviolet (DUV) technology in advanced semiconductor manufacturing — is finally on the cusp of production after years of delays. Leading-edge semiconductor manufacturers include Samsung, Intel and TSMC are planning to use EUV in volume production beginning in the next year, though concerns remain about the availability of the EUV power source and other items in the EUV supply chain, including pellicles.ASML says it has now demonstrated four-week availability of well above 85% on a number of its new NXE:3400B EUV systems and is executing several programs to improve consistent availability to over 90% in 2019.Wennink said ASML's deep-ultraviolet lithography business continues to thrive, driven largely by the memory market, which  continues to require a significant number of lithography systems at least throughout this year and into 2019. After an excellent first half of 2018, we expect the second half."After an excellent first half of 2018, we expect the second half to be stronger, with improved profitability and continued growth from Q3 to Q4,” Wennink said.For the third quarter,  ASML said it expects sales of between 2.7 billion and 2.8 billion euro (roughly $3.15 billion to $3.26 billion).
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Release time：2018-07-20 00:00 reading：1100 Continue reading>>
ASML Updates <span style='color:red'>EUV</span> Roadmap
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ASML Updates EUV Roadmap

　　SAN JOSE, Calif. — ASML showed stepwise progress in an update on the performance of its latest extreme ultraviolet (EUV) lithography system and its roadmap at the SPIE Advanced Lithography conference here. The talks showed that getting EUV into production will be a nail-biter, and keeping it useful in the next generation will require multiple field upgrades.　　Over the weekend, the NXE 3400B system delivered 140 wafers/hour with a 245-W light source integrated in a system at the company’s headquarters in the Netherlands. ASML aims to tune the light source to 250 W for throughput of 150 wafers/hour and ship it to customers before June for use on 7-nm process nodes.　　The lab demo was conducted without use of a protective pellicle on the wafers. The tests exposed a full field with 96 fields using a dose of 20 mJ/cm2.　　A test using an 83% transmissive pellicle reached 100 WPH. ASML targets a 90% transmissive pellicle with 125-WPH throughput that can withstand a 300-W light source.　　In its efforts to reduce defects from contaminating particles, ASML is working in parallel on the pellicle and a cleaner scanner that doesn’t need a pellicle. Last year, it eliminated all but six particles in a run of 10,000 wafers and aims to reduce it to one particle per 10,000 wafers next year.　　The company targets a greater-than-90% uptime for the system by 2018–2019, when it should be in volume production. A day earlier, a Globalfoundries executive said that productivity levels were the key gating item on the first commercial use of the systems.　　To meet the needs of 5-nm nodes, ASML plans three upgrades to the system delivered over the next two years.　　Late this year, ASML aims to deliver a so-called overall and focus improvement package that enables overlays down to 1.7 nm, slightly below the required 1.9-nm target for 5 nm. In mid-2019, it plans a productivity enhancement package that boosts throughput to 145 WPH.　　ASML is considering a model 3400C that it could deliver in 2020 with additional improvements, boosting throughput to 155 WPH. Details of the system are still under discussion with the small handful of big chip vendors who would be its users.　　The NXE 3400B, large and ambitious as it is, is dwarfed by emerging plans for a follow-on tool nearly twice its size.　　The 0.55-NA system aims to use larger optics, a higher-power light source, and faster internal pathways to kick out a maximum of 185 WPH while printing features with dimensions as small as 8 nm. If successful, the new system could print in one pass the kind of 3-nm features that today’s 3400B is expected to need three passes to create.　　A talk on the new system here gave only a few glimpses at its progress but rammed home the point of its gigantic scope and scale. Optics maker Carl Zeiss SMT is now installing the first metrology system — the size of a small submarine — needed to make the system’s new and significantly larger lenses.　　Zeiss is now constructing multiple buildings to house manufacturing for the optics. In November, it got a pledge of a $1.9 billion investment from ASML as part of their collaboration.　　Meanwhile, engineers have finished their feasibility study and started design work on the system. It includes stands to help slide away a top module and remove a vacuum hull for servicing and upgrades, a process that, in an animation, looked akin to replacing an engine in a two-story locomotive.　　Among other interesting details, the scanner requires a wafer cooling subsystem. That’s because it aims to focus two to three times more power on the wafer than the 3400B.　　The subsystem is needed to ensure that heat generated by the light source deforms a wafer by no more than a nanometer while printing. Without it, a wafer could warp as much as 11.4 nm — larger than some of the features that it prints.　　Jan Van Schoot, who leads the high-NA design for ASML, said that he sees no change in the existing power density needed for a protective pellicle.　　Separately, ASML and Imec are exploring a stitching subsystem. It would knit two slightly deformed test images into one more perfect one to print. The process aims to speed throughput and help make increasingly large server chips.　　The stitching concept has long been studied but never successfully implemented, noted one audience member in a Q&A session.　　“Our study is ongoing and we may be showing more than we intend to do,” said Van Schoot. “We know it’s hard to do, so if we can’t implement it, we envision [that] less critical structures will be made at crossover points.”
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Release time：2018-03-01 00:00 reading：1553 Continue reading>>
<span style='color:red'>EUV</span> Defects Cited in 5-nm Node
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EUV Defects Cited in 5-nm Node

　　SAN JOSE, Calif. — Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.　　The news comes as Globalfoundries, Samsung, and TSMC are racing to rev EUV systems up to high availability with 250-W light sources for 7-nm production next year. The defects show that there’s no panacea for the increasing costs and complexity of making semiconductors.　　The latest EUV scanners can print the 20-nm-and-larger critical dimensions that foundries plan at 7 nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said in a talk at the SPIE Advanced Lithography conference here.　　Optimists such as McIntyre believe that a basket of solutions will emerge for the so-called stochastic effects. Some skeptics see the results as one more reason to doubt that the expensive and long-delayed EUV systems will become mainstream tools for chipmakers.　　A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.　　The latest defects are cropping up at critical dimensions around 15 nm needed to make 5-nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won’t be available until about 2024, it said at the event last year.　　The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.　　McIntyre outlined the challenges finding and eliminating the errors. For example, some researchers are proposing this week a standard way to measure the roughness of lines, one key to understanding the defects.　　Another issue is that it’s unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created … we’re a little ways from a full understanding of the physics, so we’re doing more experiments,” said McIntyre, noting that researchers have tested as many as 350 combinations of resists and process steps.　　“Manufacturing guys will get beat up incredibly over yield loss … if I was going to be responsible for this, I’d say it’s time to retire,” quipped one veteran lithographer during a Q&A session about the 5-nm defects.　　A Globalfoundries technologist provided a more upbeat but sober assessment in another keynote. “It’s been a lot of hard work, and there’s a lot more hard work to come,” said George Gomba, a vice president of research at GF, recalling a nearly 30-year history of work on EUV.　　Today’s NXE 3400 systems are “not meeting some roadmap conditions we desire, so there is still some uncertainty [at 7 nm]. If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors.”　　Gomba noted that the random defects at 5 nm include subtle 3D breaks and tears such as notches in lines. He also called for more work on so-called actinic systems that inspect EUV masks before lithographers cover them with protective pellicles.　　“To get full use of EUV, we will need actinic inspection systems [still in development], maybe complementing e-beam mask inspection systems” that are available today.　　In an interview, Borodovsky said that another factor that may be contributing to the 5-nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said that he supports work on direct e-beam writers because the complex phase-shift masks that EUV uses ultimately will balloon to eight times the price of today’s immersion masks.　　Multibeam, a company formed by Lam Research founder David Lam, recently snagged $35 million in government funding for his e-beam technology. He hopes to have commercial systems in 2.5 years for niche applications, but versions suitable for high-volume manufacturing will take much longer, said Lam.　　By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, said Borodovsky. Experimental chips using memory arrays with embedded computing elements could be more fault-tolerant, citingIBM’s True North chip and work by HP Labs with memristors.
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Release time：2018-02-28 00:00 reading：1150 Continue reading>>
Qualcomm Taps Samsung's 7nm <span style='color:red'>EUV</span> for 5G
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Qualcomm Taps Samsung's 7nm EUV for 5G

　　SAN FRANCISCO — Qualcomm said it will continue to work with longtime foundry supplier Samsung Electronics on Snapdragon 5G chipsets using Samsung's 7nm Low Power Plus (LPP) process technology with extreme ultraviolet (EUV) lithography.　　Samsung aims to take the lead in putting long-delayed EUV into production, with plans to use it in its 7nm LPP process starting in the second half of this year. Other leading-edge chip makers-- including Intel, TSMC and Globalfoundries--are targeting EUV production sometime in 2019.　　Qualcomm (San Diego) said using the 7nm LPP EUV process technology for Snapdragon 5G will give the chips a smaller footprint, providing handset OEMs with space to support larger batteries or slimmer designs. The process technology and design of the Snapdragon chips is expected to result in significant improvements in battery life, Qualcomm said.　　The 7nm LPP process offers up to a 40 percent increase in area efficiency with 10 percent higher performance or up to 35 percent lower power consumption compared to the foundry's 10nm FinFET technology, Samsung said.　　Samsung has been building chips for Qualcomm for more than 10 years. While the announcement that Qualcomm will use Samsung's 7nm LPP process technology for its 5G Snapdragon chips is hardly unexpected, the news does demonstrate that the relationship between the two companies remains strong after the Nikkei news service reported late last year that Qualcomm would move some of its modem chip production from Samsung to rival TSMC, The announcement is also a vote of confidence for EUV technology, which after decades of development finally appears poised for use in semiconductor production.　　"This collaboration is an important milestone for our foundry business as it signifies confidence in Samsung’s leading process technology," said Charlie Bae, executive vice president of Samsung's foundry sales and marketing team, in a statement.　　Samsung maintains that its 7LPP EUV technology involves less process complexity and will offer higher yield compared to its 10nm FinFET technology.
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Release time：2018-02-26 00:00 reading：1100 Continue reading>>
<span style='color:red'>EUV</span>, 7-nm Roadmaps Detailed
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EUV, 7-nm Roadmaps Detailed

　　Extreme ultraviolet lithography (EUV) is set to enable 10-nm and 7-nm process nodes over the next few years, but significant work is still needed on photoresists to enable 5-nm chips, according to an analysis released at the Industry Strategy Symposium here.　　At the same time, EUV maker ASML announced that it shipped 10 EUV systems last year and will ship 20 to 22 more this year. The systems will have, or at least support, a 250-W laser light source needed to produce 125 wafers/hour.　　“The main pieces for EUV at 7 nm are in place, and we will see some volume of wafers this year … but photoresist defects are still an order of magnitude too high for 5 nm,” said Scotten Jones, president of IC Knowledge.　　The new and expensive systems, in development more than 20 years, help make the fine features needed for next-generation chips and reduce the time required to make them. They will first be used on logic chips such as microprocessors and later applied to DRAMs but are not needed by today’s 3D NAND flash chips, said Scotten.　　“EUV provides a tremendous reduction in cycle time and edge placement errors … but not much cost reduction, at least initially. There are so many other benefits that even if the cost is neutral, it still makes sense.”　　Jones expects that ASML will ship another 70 systems in 2019–2020. That’s enough to support production nodes that he detailed in the works at Globalfoundries, Intel, Samsung, and TSMC.　　ASML has plans in place to increase uptime of the systems from about 75% today to 90%, a top concern for lithographers, said Jones. In addition, he expressed confidence that the company will release in time a pellicle needed to protect some EUV wafers from contamination.　　To enable resists for 5 nm, “we have 12 to 18 months to make a big improvement. The industry will run lots of wafers next year, and that will help,” said Jones, estimating that fabs will make nearly 1 million EUV wafers in 2019, and 3.4 million by 2021.　　ASML aims to boost the 145 wafers/hour throughput that it can get with its 250-W light source to 155 w/h in 2020. It has demonstrated a 375-W light source working in the lab, said Peter Jenkins, ASML’s vice president for corporate strategy and marketing, in a talk here.　　The company’s pellicle passes through 83% of light today and withstands a 245-W light source over 7,000 wafer exposures. However, the most aggressive 7-nm nodes need a 90% transmission used with a 250-W or greater light source.　　One of the most interesting parts of Jones’ talk was a detailed analysis of 10-, 7-, and 5-nm nodes. TSMC qualified last fall a 7-nm process that is ramping now using existing optical steppers. Globalfoundries will ramp a similar process later this year, he said.　　Both companies plan to ramp early next year a second-generation 7-nm process using EUV to make contacts and vias, reducing 15 optical layers to five EUV layers. The process does not provide a shrink, but it shortens cycle times and does not need a pellicle.　　GF announced last June its 2019 plan for 7 nm with EUV. “TSMC has privately told customers that they will do this, too,” said Jones.　　Chipmakers will probably have to use 30-ml/cm2 doses of resists, higher than the 20 ml/cm2that they target. They also will likely have to use e-beam systems to insect masks for defects rather than more accurate actinic systems still in the works that look for defects using the same 13.5-mm wavelength as the EUV systems, said Jones.　　In addition to the work with cuts and vias, GF, Samsung, and TSMC plan 7-nm variants that use EUV with a pellicle to make a first metal layer. These processes will provide a shrink and reduce 23 optical layers to nine EUV layers.　　This is the approach that Samsung will use for its first 7-nm node, called 7LPP, due early next year. TSMC will call its version 7FF+ and ramp it in mid-2019, and GF will follow with its 7LP+ late next year, said Jones.　　The 10-nm process that Intel is currently ramping using optical steppers offers similar density to what its rivals plan with their best 7-nm variants, said Jones. He expects that Intel will adopt EUV for a 10-nm+ upgrade in 2019.　　Samsung and TSMC are already talking about 5-nm processes that could be available before the end of 2019. They could be the first to use EUV for 1D metal layers. The processes could use EUV to reduce up to five cut masks for FinFETs down to one cut mask if better resists emerge, he said.　　Separately, Jenkins said that ASML completed the optics design for its follow on EUV systems supporting a high numerical aperture, and its overall design is “well along.” The company announced in late 2016 plans for the system that should be in volume production in 2024.　　Although EUV is a big milestone for enabling the semiconductor industry to make smaller chips, it is not expected to disrupt existing markets for chipmaking equipment and gear. Fabs will continue to need lots of existing capital equipment and supplies in tandem with EUV for future process nodes, said Jones.
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Release time：2018-01-19 00:00 reading：1110 Continue reading>>
<span style='color:red'>EUV</span> Backlog Grows as ASML Sets Sales Record
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EUV Backlog Grows as ASML Sets Sales Record

　　Lithography system provider ASML posted strong fourth quarter results, capping a year in which it posted record sales and shipped 10 next-generation extreme ultraviolet (EUV) lithography tools.　　Oft-delayed EUV is finally on the cusp of being inserted into production, with some leading-edge chip makers planning to use it late this year or early next.　　Peter Wennink, ASML's president and CEO, said "preparations for inserting EUV into high-volume chip manufacturing shifted into a higher gear" in 2017.　　ASML recorded EUV revenue for the year of 1.1 billion euros (about $1.34 billion) and picked up an additional 10 EUV system orders during the fourth quarter, exiting the year with a new high water EUV backlog of 28 systems.　　In all, ASML reported 2017 sales of 9.05 billion euro (about $11.04 billion) up 33 percent from 2016. The company posted a profit for the year of 2.12 billion euro (about $2.59 billion), up 44 percent from 2016.　　In the fourth quarter, ASML had total sales of 2.56 billion euros (about $3.12 billion), up 4 percent from the third quarter. The company reported a net income for the quarter of 644 million euros (about $786 million), up 16 percent from the third quarter.　　Wennink said ASML shipped two EUV systems earlier than expected in the fourth quarter, as industry strength prompted customers to ask for earlier delivery of both EUV and optical lithography systems.　　ASML also reported that it increased system sales to China by more than 20 percent from 2016 as the company continued to support China's expanding semiconductor industry. Alongside shipments to mainland fabs operated by non-Chinese customers, it is also planning to ship to five domestic Chinese customers in 2018.　　Shipments of optical lithography tools also grew substantially in 2017. The company said optical lithography system shipments increased by 21 percent over 2016, reaching 161 systems.　　ASML said it expects first quarter sales to be about 2.2 billion euro (about $2.7 billion).
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