112G, PCIe Gen4 Highlight <span style='color:red'>DesignCon</span> 2018
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112G, PCIe Gen4 Highlight DesignCon 2018

　　DesignCon has always been a favorite because it's where you get to see the latest technology that will go into the latest technology. The highest-speed digital signals start here and make their way into data centers, long-haul networks, and short reaches across PCBs. At DesignCon 2018, a great deal of talk went into 112-Gbps links, called 112G.　　Although 112G was all the rage, 56G was still in abundance. The difference is that NRZ signaling has finally reached its limit at 56G. At 112G, it's all PAM4. That's not to say that PAM4 isn't used in 56G, it's just that at 112G, it's all about PAM4.　　Below, you'll find photos and video from several 112G demonstrations, which cover connectors and test equipment. Page 2 contains demonstrations on PCIe Gen4 test equipment. Page 3contains pattern generators and related test equipment from two small companies.　　112G demonstrations　　Connector and test-equipment companies have hit the ground (no pun intended) running with 112G demonstrations.　　Samtc high-speed cables　　Samtec's 112-Gbps demonstration featured its latest backplane cables. Photo by Martin Rowe.　　In the video below, Samtec's Scott McMorrow explains how engineers get 112-Gbps transmission using PAM4.　　TE Connectivity demonstrated a board that can run 112 Gbps using PAM4 modulation. It's being used for measurements as part of the next generation of Optical Internetworking Forum Common Electrical Interface (OIF CEI) standards. For more detail, see High-speed digital: 112 is the new 56.　　TE Connectivity developed a board for making measurements on 112-Gbps backplane connectors and PCB traces. Photo by Martin Rowe.　　With PAM4, 112G uses the same bandwidth as 56G NRZ. High-end oscillosocpes and signal analyzers can already handle the bandwidth, which is 28 GHz. That's because PAM4 provides two bits per symbol, and data is clocked on both rising and falling edges. Here, Keysight Technologies demonstrates 112-Gbps PAM4.　　Keysight Technologies 112-Gbps demonstration used a Credo IC and a signal analyzer. Photo by Martin Rowe.　　PCI Express Gen 4, which operates at 16 GT/s (T = transfers), became a reality in 2017. Test companies need to be on top of such developments. In this video, we see a test setup from Teledyne LeCroy. Not to be outdone, rival Tektronix also demonstrated its PCIe Gen4 test equipment.　　Tektronix demonstrated PCIe Gen4 test with its BERTScope bit-error-rate tester. Photo by Martin Rowe.　　BERTScope (see previous page) came to Tektronix when the company acquired SyntheSys Research in 2010. Synthesys founders Jim and Tom Waschura are back, having started BitWise Labs, which also exhibited at DesignCon. The company has developed a pattern generator, PAM4 combiner and decombiner, a bit-error-location analyzer, and a time-domain reflectometer, named STEPScope.　　BitWise Labs, started by Jim and Tom Waschura, demonstrated a pattern generator, PAM4 combiner and decombiner, a bit-error locator, and a time-domain reflectometer. Photo by Martin Rowe.　　BitWise equipment can be operated over a USB link or wirelessly, as demonstrated here with a tablet.　　You can operate test equipment from BitWise Labs with a tablet. Photo by Martin Rowe.　　Adsantec, another small California company, also demonstrated a pattern generator and combiner, showing both 32-Gbaud and 64-Gbaud signals.　　Adsantec　　Adsantec's pattern generators and combiners generate digital data streams up to 64-Gbaud PAM4. Photo by Martin Rowe.
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Release time：2018-02-13 00:00 reading：1613 Continue reading>>
<span style='color:red'>DesignCon</span>: SI, PI, EMI Have a Future Together
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DesignCon: SI, PI, EMI Have a Future Together

　　Santa Clara, Calif. — Our insatiable appetite for more data drives engineers to develop ever-faster links. Each speed increase brings with it a new set of engineering problems to solve. In the early 2000s, 1 Gbps was fast. Today, engineers are developing connections that will run at 112 Gbps. Some even have an eye on the next speed jump.　　Each speed increase results in new issues in signal integrity (SI), power integrity (PI), and electromagnetic interference (EMI). No longer can engineers designing high-speed digital systems specialize in one discipline without some knowledge of the other two. With that in mind, five engineers presented their views on the future of SI/PI/EMI on Jan. 30, 2018, at DesignCon in a panel-based keynote address.　　Moderator Steve Sandler, managing director of Picotest, took the audience through some of his power systems designs and looked at past predictions that came true — or didn't.　　Eric Bogatin, the signal integrity evangelist, told the audience, "The blessing of each new technology is the killer app, but they come with unintended consequences." Looking into his "crystal ball," Bogatin sees several possible killer apps. Among them are visual interfaces such as those that will come from AI and VR, but the list goes on to include human-machine interfaces and brain-computer interfaces.　　It's impossible to get through this kind of technical talk without hearing about IoT. Bogatin sees it as the fusion of technology and the internet, but it's not just engineers getting into IoT. "Don't forget about makers and enthusiasts," he said. "They're generally not engineers, but they are building things with technology. I love the maker movement."　　As I later discussed with Bogatin, however, the problem with makers comes from when things don't work, for many lack the tools — both educational and test equipment — to troubleshoot their systems. That puts additional pressure on the engineers developing hardware for makers to get the SI, PI, and EMI right. Unfortunately, getting that much right can still lead to problems at the system level.　　Oracle's Istvan Novak took a more DesignCon approach in his talk. He started by looking back at predictions that he made in 2007, when he thought that we wouldn’t need bypass capacitors by now. At DesignCon 1995, he predicted that by today, computers would look like "steamy, hairy, golf balls," small, hot, and full of wires from parallel buses. "The only one I got right was that computers and their chips run hot," he admitted.　　As for the future of power integrity, Novak sees DC/DC converters being mounted directly on IC packages. This minimizes impedance and minimizes losses in power delivery. Such development might actually lead to the elimination of bypass capacitors.　　Neves focused on today's signal-integrity issues, claiming that signal integrity needs to be simplified for engineers to solve SI problems. A 50-Ω system can't deviate by more than 2 Ω and still be viable. Many engineers don't understand that. "Engineers need to learn electromagnetics and how to make measurements," he claimed. "Instead of leaving work early on Friday afternoons, stay and teach yourself how to make measurements. That's how I learned to use a vector-network analyzer (VNA)."　　"What do engineers need to do now?" asked Sandler of the other panelists.　　Bogatin: Understand SI, PI, and EMI, but how do you get experience? Attend conferences and attend technical sessions; watch and attend seminars.　　Novak: Education is key. You need knowledge in several disciplines. Companies must do a better job with integration of systems and solve SI, PI, and EMI problems.　　Wyatt: After a career in EMI, I'm learning about power integrity. Designers need to understand grounding and shielding. Learn about electromagnetic fields and the move on PCBs. Designers need this kind of training.　　Neves: It's all about commitment. Buy books, attend seminars, read papers, and commit to taking the time to learn.　　As Prof. Woodie Flowers said, "You must continue to learn throughout your life, so keep it up. Learn to learn."
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Release time：2018-02-05 00:00 reading：1288 Continue reading>>

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