<span style='color:red'>DARPA</span> Takes Chip Route to ‘Unhackable’ Computers
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DARPA Takes Chip Route to ‘Unhackable’ Computers

　　Cybersecurity experts have long preached that the only way to make computers “unhackable” is with on-chip hardware, but no one has done it yet. The Defense Advanced Research Agency (DARPA) is pursuing the goal under such efforts as its High-Assurance Cyber Military Systems program and the Cyber Grand Challenge. Most recently, under its System Security Integrated through Hardware and Firmware (SSITH) program, DARPA has doled out $3.6 million to the University of Michigan for continued development of a microarchitecture that its creators say is unhackable.　　Instead of the usual “patch and pray” software method of plugging security holes, DARPA wants to leverage new technologies to develop integrated circuits that are inherently impervious to software “end runs,” said Linton Salmon, program manager at the agency’s Microsystems Technology Office.　　Intel has provided on-chip V-Pro security hardware in its Xeon microprocessor family for years. But DARPA is looking for a higher degree of protection, especially for military field computers, as a hardware security breach in the field could put soldiers’ lives at risk.　　DARPA’s stated goal of “hack resistance” appears to hedge a bit on whether truly unhackable hardware is achievable. But Michigan EECS professor Todd Austin, lead researcher on the project, claims his team’s approach, called Morpheus, achieves hack-proof hardware by changing the internal codes once a second. Austin likens Morpheus’ defenses to requiring a would-be attacker to solve a new Rubik’s Cube every second to crack the chip’s security. In this way, the architecture provides the maximum possible protection against intrusions, including hacks that exploit zero-day vulnerabilities, or those that cybersecurity experts have yet to discover. Morpheus thereby provides a future-proof solution, Austin said.　　Morpheus works its magic by constantly changing the location of the protective firmware with hardware that also constantly scrambles the location of stored passwords. Because passwords are encrypted — which takes time for hackers to decode — even the fastest hacker cannot find the vulnerability a second time after decryption.　　The technique used in Morpheus is already being used by military computers today in software. By casting key operations in hardware, however, Austin believes he can eliminate all classes of known vulnerabilities: permissions and privileges, buffer errors, resource management, information leakage, numeric errors, crypto errors, and code injection.　　Austin and his team will use the DARPA funding to design the hardware version of the Morpheus protection algorithm into affordable hardware in order to limit the cost impact of unhackable microprocessors. Morpheus is one of nine projects DARPA has funded under SSITH.
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Release time：2017-12-26 00:00 reading：1294 Continue reading>>
<span style='color:red'>DARPA</span> Heeds Moore’s Wisdom
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DARPA Heeds Moore’s Wisdom

　　Gordon Moore, whose eponymous law has guided the industry for decades, supplied the ideas behind the Defense Advanced Research Projects Agency’s newly announced additions to its Electronics Resurgence Initiative (ERI), according to Bill Chappell, director of DARPA’s Microsystems Technology Office (MTO). DARPA this week posted three broad agency announcements (BAAs) that describe six new programs to address the problems that Moore 50 years ago predicted would loom at the end of the current silicon roadmap. The programs will collectively add $75 million a year to the ERI’s cost, bring the projected annual tally for the four-year initiative to $216 million. The agency is calling the new programs its Page 3 Investments as a tribute to Moore, who described the research challenges on page 3 of “Cramming More Components onto Integrated Circuits,” published in Electronics in April 1965 and excerpted here.　　Heat Problem　　Will it be possible to remove the heat generated by tens of thousands of components in a single silicon chip?　　If we could shrink the volume of a standard high-speed digital computer to that required for the components themselves, we would expect it to glow brightly with present power dissipation. But it won’t happen with integrated circuits. Since integrated electronic structures are two dimensional, they have a surface available for cooling close to each center of heat generation. In addition, power is needed primarily to drive the various lines and capacitances associated with the system. As long as a function is confined to a small area on a wafer, the amount of capacitance which must be driven is distinctly limited. In fact, shrinking dimensions on an integrated structure makes it possible to operate the structure at higher speed for the same power per unit area.　　Day of Reckoning　　Clearly, we will be able to build such component-crammed equipment. Next, we ask under what circumstances we should do it. The total cost of making a particular system function must be minimized. To do so, we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array. Perhaps newly devised design automation procedures could translate from logic diagram to technological realization without any special engineering. It may prove to be more economical to build large systems out of smaller functions which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.　　Linear Circuitry　　Integration will not change linear systems as radically as digital systems. Still, a considerable degree of integration will be achieved with linear circuits. The lack of large- value capacitors and inductors is the greatest fundamental limitation to integrated electronics in the linear area.　　By their very nature, such elements require the storage of energy in a volume. For high Q it is necessary that the volume be large. The incompatibility of large volume and integrated electronics is obvious from the terms themselves. Certain resonance phenomena, such as those in piezoelectric crystals, can be expected to have some applications for tuning functions, but inductors and capacitors will be with us for some time.　　The integrated RF amplifier of the future might well consist of integrated stages of gain, giving high performance at minimum cost, interspersed with relatively large tuning elements.　　Other linear functions will be changed considerably. The matching and tracking of similar components in integrated structures will allow the design of differential amplifiers of greatly improved performance. The use of thermal feedback effects to stabilize integrated structures to a small fraction of a degree will allow the construction of oscillators with crystal stability.　　Even in the microwave area, structures included in the definition of integrated electronics will become increasingly important. The ability to make and assemble components small compared with the wavelengths involved will allow the use of lumped parameter design, at least at the lower frequencies. It is difficult to predict at the present time just how extensive the invasion of the microwave area by integrated electronics will be. The successful realization of such items as phased-array antennas, for example, using a multiplicity of integrated microwave power sources, could completely revolutionize radar.　　According to Chappell, the ERI program will “stand on the shoulders of Moore” by extending his principles to ensure continuance of “the greatest commercial benefits and the greatest gains in defense capabilities” ever achieved.　　Chappell believes that Moore’s Law can be extended indefinitely by DARPA’s ERI initiatives, which already address materials and integration, circuit design, systems architecture, and strengthening of the fundamental-research base.　　The agency’s new Three Dimensional Monolithic System-on-a-Chip (3DSoC) program will aim at a fiftyfold improvement in computation time, while using less power, by packing processors, logic, memory, and input/output in power-saving, high-riser three-dimensional cubes. A second program, funded under the same BAA as the 3DSoC initiative, is Foundations Required for Novel Computers (FRANC), which will scrap John von Neumann’s separate data and memory functions. According to DARPA, combining data and memory functions will “overcome the memory bottleneck” of moving data from memory to the processor and back again. The effort will require development of novel materials, such as memristors; components, such as artificial neurons and synapses; and algorithms, including ones modeled on the human brain.　　The second new BAA is a two-pronged effort to redefine circuit and system specialization. The Intelligent Design of Electronic Assets (IDEA) program will look to automate design so that even nonengineers can describe the functions to be performed, with a robotic design automation system doing the work to create the design overnight. The Posh Open Source Hardware (POSH) program will support a complementary open-source verification framework to check and redesign, if necessary, even the most complicated systems-on-chip and printed-circuit boards produced by IDEA.　　The third BAA likewise comprises two programs. Software Defined Hardware (SDH) will act as a “decision assistant” for reconfigurable hardware/software that will run data-intensive algorithms for artificial-intelligence applications using application-specific ICs to handle the thousands of intelligence, surveillance, and reconnaissance sensors used in modern warfare as well as civilian Big Data applications. The complementary Domain-Specific System-on-a-Chip (DDSoC) program aims to develop multi-application hardware/software systems that users could mix and match to solve problems such as software-defined radio, which encompasses mobile communications, satellite communications, personal area networks, and all types of radar. SDR applications will emerge for electronic warfare between 2025 and 2030, according to Chappell.　　For more details, see DARPA’s slide deck on the six new directions for the ERI program.
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Release time：2017-09-18 00:00 reading：1406 Continue reading>>
<span style='color:red'>DARPA</span> Calls for Post-Moore Ideas
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DARPA Calls for Post-Moore Ideas

　　It’s “the summer of listening” for Bill Chappell, head of a $200+ million government program seeking ways to revitalize electronics. He doesn’t expect to find a replacement for Moore’s law, but he does hope to “shake things up,” creating a handful of alternatives for advancing semiconductor performance.　　“I don’t think exponential growth on a single variable [such as CMOS scaling] is achievable,” Chappell said in an interview about the Electronics Resurgence Initiative (ERI).　　“The next era we're heading into is about progress in lots of variables…hardware/software co-design, new materials and functional blocks, specialization for each app…We’re not out of ideas at all, this is a wildly interesting time where lots of creativity will make up for the march of scaling,” said Chappell, director of the microsystems group at the Defense Advanced Research Projects Agency (DARPA).　　Many industry executives heard about ERI for the first time at a June meeting Chappell hosted in Austin during the Design Automation Conference. About 60 people attended the meeting from companies including Analog Devices, ARM, Cadence, IBM, Intel, Qualcomm, Synopsys, TSMC and Xilinx.　　“It was an intro to the program for industry leaders who may not have been involved with DARPA,” said Steve Keckler, a vice president of architecture research at Nvidia, who spoke at the event about the GPU designer’s work with the agency.　　“I see ERI as an opportunity to engage a broader set of partners to bring things to market, many who haven’t collaborated with DARPA before,” Keckler said.　　This week DARPA conducted a two-day meeting in San Jose to work with chip experts and help them form partnerships. As many as 300 people attended, representing about 45 companies, 10 defense contractors and numerous universities.　　“This is the start of something with teeth behind it,” Chappell said during a break in the event.　　Earlier, DARPA hosted a meeting with defense contractors in Washington D.C. to spawn their ideas. A team of ERI program managers will package the best concepts into a formal call for proposals in September. DARPA will pick and negotiate contracts on winning projects over the following seven months before funding is released and the hard work begins.
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Release time：2017-07-21 00:00 reading：1067 Continue reading>>
<span style='color:red'>DARPA</span> Funds Development of New Type of Processor
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DARPA Funds Development of New Type of Processor

　　A completely new kind of non-von-Neumann processor called a HIVE — Hierarchical Identify Verify Exploit — is being funded by the Defense Advanced Research Project Agency (DARPA) to the tune of $80 million over four-and-a-half years. Chipmakers Intel and Qualcomm are participating in the project, along with a national laboratory, a university and a defense contractor North Grumman.　　Pacific Northwest National Laboratory (Richland, Washington) and Georgia Tech are involved in creating software tools for the processor while Northrup Grumman will build a Baltimore center that uncovers and transfers the Defense Departments graph analytic needs for the what is being called the world's first graph analytic processor (GAP).　　"When we look at computer architectures today, they use the same [John] von Neumann architecture invented in the 1940s. CPUs and GPUs have gone parallel, but each core is still a von Neumann processor," Trung Tran, a program manager in DARPA’s Microsystems Technology Office (MTO), told EE Times in an exclusive interview.　　"HIVE is not von Neumann because of the sparseness of its data and its ability to simultaneously perform different processes on different areas of memory simultaneously," Trung said. "This non-von-Neumann approach allows one big map that can be accessed by many processors at the same time, each using its own local scratch-pad memory while simultaneously performing scatter-and-gather operations across global memory."　　Graph analytic processors do not exist today, but they theoretically differ from CPUs and GPUs in key ways. First of all, they are optimized for processing sparse graph primitives. Because the items they process are sparsely located in global memory, they also involve a new memory architecture that can access randomly placed memory locations at ultra-high speeds (up to terabytes per second).　　Today's memory chips are optimized to access long sequential locations (to fill their caches) at their highest speeds, which are in the much slower gigabytes per second range. HIVEs, on the other hand, will access random eight-byte data points from global memory at its highest speed, then process them independently using their private scratch-pad memory. The architecture is also specified to be scalable to up to however many HIVE processors are needed to perform a specific graph algorithm.　　"Of all the data collected today, only about 20 percent is useful — that's why its sparse —making our eight-byte granularity much more efficient for Big Data problems," said Tran.　　Together, the new arithmetic-processing-unit (APU) optimized for graph analytics plus the new memory architecture chips are specified by DARPA to use 1,000-times less power than using today's supercomputers. The participants, especially Intel and Qualcomm, will also have the rights to commercialize the processor and memory architectures they invent to create a HIVE.　　The graph analytics processor is needed, according to DARPA, for Big Data problems, which typically involve many-to-many rather than many-to-one or one-to-one relationships for which today's processors are optimized. A military example, according to DARPA, might be the the first digital missives of a cyberattack. A civilian example, according to Intel, might be all the people buying from Amazon mapped to all the items each of them bought (clearly delineating the many-to-many relationships as people-to-products).　　"From my standpoint, the next big problem to solve is Big Data, that today is analyzed by regression which is inefficient for relations between data points that are very sparse," said Tran. "We found that the CPU and GPU leave a big gap between the size of problems and the richness of results, whereas graph theory is a perfect fit for which we see an emerging commercial market too."
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Release time：2017-06-12 00:00 reading：1108 Continue reading>>

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