Samsung’s Big Semi Capex Spending Keeps Pressure on Competition

Release time:2018-12-03
author:Ameya360
source:IC Insights
reading:2636

Samsung’s two-year capex spending of $46.8 billion nearly matches the combined two-year capex spending of $48.4 set by Intel and TSMC.

IC Insights revised its outlook for total semiconductor industry capital spending and presented its forecast of semiconductor capex spending for individual companies in its November Update to The McClean Report 2018, which was released earlier this month.

Samsung is expected to have the largest capex budget of any IC supplier again in 2018.  After spending $24.2 billion for semiconductor capex in 2017, IC Insights forecasts that Samsung’s spending will edge slightly downward, but remain at a very strong level of $22.6 billion in 2018 (Figure 1).  If it comes in at this amount, Samsung’s two-year semiconductor capital spending will be an astounding $46.8 billion.

Samsung’s Big Semi Capex Spending Keeps Pressure on Competition

Figure 1

As seen in Figure 1, Samsung’s semiconductor capital outlays from 2010, the first year the company spent more than $10 billion in semiconductor capex, through 2016 averaged $12.0 billion per year.  However, after spending $11.3 billion in 2016, the company more than doubled its 2017 capex budget.  The fact that Samsung’s continued its strong capex spending in 2018 is just as impressive.

IC Insights believes that Samsung’s massive spending outlays in 2017 and 2018 will have repercussions far into the future.  One effect that has already begun is a period of overcapacity in the 3D NAND flash market.  This overcapacity situation is due not only to Samsung’s huge spending for 3D NAND flash, but also from spending by competitors (e.g., SK Hynix, Micron, Toshiba, Intel, etc.) that attempt to keep pace in this market segment.

With the DRAM and NAND flash memory markets showing strong growth through the first three quarters of 2018, SK Hynix ramped up its capital spending this year.  In 1Q18, SK Hynix said that it intended to increase its capex spending by “at least 30%” this year.  In the November Update, IC Insights forecasts that SK Hynix will see a 58% surge in its semi capex spending.  The increased spending by SK Hynix this year is focused primarily on bringing new capacity online at two of its large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea, and the expansion of its huge DRAM fab in Wuxi, China.  The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original start date of early 2019.

Overall, IC Insights’ now forecasts total semiconductor industry capital spending will climb 15% to $107.1 billion this year, the first time that annual industry capex is expected to top $100.0 billion.  Following the industry-wide growth this year, semiconductor capex is expected to decline 12% in 2019 (Figure 2).

Samsung’s Big Semi Capex Spending Keeps Pressure on Competition

Figure 2

Given that the current softness in the memory market is expected to extend into at least the first half of next year, the combined capital spending by the three largest memory suppliers—Samsung, SK Hynix, and Micron—is forecast to drop from $45.4 billion in 2018 to $37.5 billion in 2019, a decline of 17%.

In total, the top five spenders, which are expected to represent 66% of total outlays this year, are forecast to cut their capital spending by 14% in 2019 with the remaining semiconductor industry companies registering a 7% decline.

("Note: The information presented in this article is gathered from the internet and is provided as a reference for educational purposes. It does not signify the endorsement or standpoint of our website. If you find any content that violates copyright or intellectual property rights, please inform us for prompt removal.")

Online messageinquiry

reading
Samsung Starts Shipping Industry-First HBM4E Samples 3 Months After HBM4 Ramp; Performance Up 20%+
  Just months after rolling out HBM4 shipments in early 2026, Samsung has begun providing samples of the industry’s first 12-layer HBM4E to major global partners, according to the company’s latest press release.  Given that HBM4 shares the same 1c DRAM process and 4nm base die architecture as HBM4E, and is already in mass production, industry observers suggest the newly shipped HBM4E samples are also well positioned to transition into mass production. Samsung adds that it plans to proceed with HBM4E mass production in line with client-specific timelines.  Meanwhile, Samsung is also expanding mass production and supply of HBM4, which became the world’s first HBM4 to enter mass production and shipment in February. In December last year, Samsung’s HBM4 received top-tier evaluation after demonstrating an industry-leading 11.7Gbps speed in System-in-Package (SiP) testing, the final certification stage, the company adds.  According to News1, the latest development makes Samsung the first to supply HBM4E. Industry observers cited by the report also noted that starting from HBM4, customer-specific design flexibility and stable large-scale supply capabilities will become even more critical. Against this backdrop, Samsung’s integrated strengths across memory, foundry, and advanced packaging are expected to stand out even more clearly, the report adds.  HBM4E Upgrade with 20% Performance Boost, 30% Higher Capacity  In terms of performance, Samsung notes that HBM4E marks a notable upgrade over the previous generation, offering a stable 14Gbps pin speed that can scale up to 16Gbps for more demanding AI workloads. Compared with HBM4, the new memory delivers over 20% higher performance and reaches bandwidth of up to 3.6TB/s per stack, significantly improving compute efficiency for large language models (LLMs) and next-generation AI systems.  Additionally, Samsung’s 12-layer HBM4E is currently offered in a 48GB capacity, which is more than 30% higher than the previous generation. The company plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) variants to better align with diverse customer requirements as well.  From an efficiency standpoint, Samsung highlights that advanced low-power design techniques and an optimized packaging architecture have improved energy efficiency by 16% while reducing thermal resistance by more than 14% compared with the previous generation.  HBM4E Progress Among Rivals  Meanwhile, progress from SK hynix and Micron in HBM4E has come under closer market scrutiny following Samsung’s advances. According to Yonhap News Agency, SK hynix had initially planned to begin HBM4E sample shipments in the second half of this year, but recent reports indicate smoother-than-expected development progress, bringing forward its timeline.  On the other hand, Micron said its first HBM4E product will follow JEDEC standards, with mass production ramp-up targeted for 2027, according to STOCK Analysis.
2026-05-29 10:18 reading:332
Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%
  Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.  The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.  More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.  The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.  Commercialization Timeline Remains Unclear  Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.  Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.  SK hynix Advances Mobile AI Packaging  SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.  Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.
2026-05-15 10:49 reading:693
[News] Samsung Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed
  According to TechNews’ report, TSMC and Samsung fiercely compete in the semiconductor foundry sector. Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 mobile processor might adopt a dual-foundry strategy with TSMC and Samsung manufacturing simultaneously.  However, according to the latest industry information, due to Samsung’s conservative expansion plan for next year’s 3nm production capacity and unstable yields, Qualcomm has officially canceled the plan to utilize Samsung for next year’s processors. The dual-sourcing model is now postponed until 2025.  Samsung began mass production of its first-generation 3nm GAA (SF3E) process at the end of June last year, marking Samsung’s initial use of the innovative GAA architecture for transistor technology. The second-generation 3nm process, 3GAP (SF3), will utilize the second-generation MBCFET architecture, optimizing it based on the foundation of the first-generation 3nm SF3E. It is expected to enter mass production in 2024.  The dual-foundry strategy for Qualcomm was initially leaked by the reputable source Revegnus via the X platform (formerly Twitter). It was mentioned that the Snapdragon 8 Gen 4 processor would adopt TSMC’s 3nm (N3E) process, while Samsung’s 3GAP process would be used for the Snapdragon 8 Gen 4 supplying Samsung’s Galaxy series smartphones. Other sources suggested that due to limited capacity at TSMC’s 3nm production, Qualcomm had to seek Samsung as an alternative chip foundry.  As a result, Qualcomm originally anticipated dual-foundry production with both TSMC and Samsung in 2024, with hopes of being the first customer for the 3GAP process. However, considering Samsung’s conservative 3nm production capacity plan for next year and the instability in yields, Qualcomm decided to scrap the plan and exclusively rely on TSMC, pushing the dual-foundry strategy to 2025.  Currently, TSMC’s 3nm process technology capacity is on the rise, with expectations that by the end of 2024, monthly production capacity will reach 100,000 wafers, and the revenue contribution will increase from the current 5% to 10%.
2023-12-01 14:48 reading:4045
Samsung cuts NAND flash memory production
  • Week of hot material
  • Material in short supply seckilling
model brand Quote
BD71847AMWV-E2 ROHM Semiconductor
RB751G-40T2R ROHM Semiconductor
CDZVT2R20B ROHM Semiconductor
MC33074DR2G onsemi
TL431ACLPR Texas Instruments
model brand To snap up
BP3621 ROHM Semiconductor
STM32F429IGT6 STMicroelectronics
IPZ40N04S5L4R8ATMA1 Infineon Technologies
ESR03EZPJ151 ROHM Semiconductor
BU33JA2MNVX-CTL ROHM Semiconductor
TPS63050YFFR Texas Instruments
Hot labels
ROHM
IC
Averlogic
Intel
Samsung
IoT
AI
Sensor
Chip
About us

Qr code of ameya360 official account

Identify TWO-DIMENSIONAL code, you can pay attention to

AMEYA360 weixin Service Account AMEYA360 weixin Service Account
AMEYA360 mall (www.ameya360.com) was launched in 2011. Now there are more than 3,500 high-quality suppliers, including 6 million product model data, and more than 1 million component stocks for purchase. Products cover MCU+ memory + power chip +IGBT+MOS tube + op amp + RF Bluetooth + sensor + resistor capacitance inductor + connector and other fields. main business of platform covers spot sales of electronic components, BOM distribution and product supporting materials, providing one-stop purchasing and sales services for our customers.

Please enter the verification code in the image below:

verification code