Samsung, Xilinx Back Programmable Chip Startup

发布时间:2017-09-30 00:00
作者:Ameya360
来源:Dylan McGrath
阅读量:4587

  Programmable logic vendor Xilinx Inc. and the venture capital arm of Samsung Electronics were among a handful of firms to provide $9.5 million in funding to Efinix, a developer of silicon-based programmable product platforms based in Silicon Valley.

  Efinix (Santa Clara, Calif.), founded in 2012, has raised a total of $16 million. The company says its Quantum programmable technology delivers a four-fold power, performance and area advantage over traditional technologies. The technology is based on what Efinix calls an XLR (exchangeable logic and routing) cell that can function as either a look-up table (LUT)-based logic cell or  routing switch encoded with a scalable, flexible routing structure.

  According to Efinix, this technology improves the active area utilization by 4X compared with traditional FPGAs, resulting in up to 4X area efficiency and 2X power consumption advantage.

  According to the company's website, Efinix is currently developing silicon products based on Quantum and expects to begin sampling in Decemeber of this year.

  The funding round was led by Xilinx and Hong Kong X Technology Fund, an investment firm supported by Sequoia Capital China and focused on fast-growing tech firms. Samsung Ventures, Hong Kong Inno Capital and Brizan Investments also participated in the funding round, according to Efinix.

  Sammy Cheung, co-founder, CEO, and president of Efinix, said in a press statement that the company plans to use the funding to launch a number of joint development projects in the coming months in addition to the chips.

  "High-volume applications and markets are prime targets for our Quantum-accelerated products," Cheung said.

  Also in the press statement, Salil Raje, senior vice president of the software and IP products group at Xilinx, said, "Efinix’s solution can address a wide variety of applications that are typically not served by today’s FPGAs."

  An unnamed representative from Samsung Ventures said Samsung envisions many applications that feature Quantum technology embedded inside ASICs, ASSPs or FPGAs.

(备注:文章来源于网络,信息仅供参考,不代表本网站观点,如有侵权请联系删除!)

在线留言询价

相关阅读
Samsung Starts Shipping Industry-First HBM4E Samples 3 Months After HBM4 Ramp; Performance Up 20%+
  Just months after rolling out HBM4 shipments in early 2026, Samsung has begun providing samples of the industry’s first 12-layer HBM4E to major global partners, according to the company’s latest press release.  Given that HBM4 shares the same 1c DRAM process and 4nm base die architecture as HBM4E, and is already in mass production, industry observers suggest the newly shipped HBM4E samples are also well positioned to transition into mass production. Samsung adds that it plans to proceed with HBM4E mass production in line with client-specific timelines.  Meanwhile, Samsung is also expanding mass production and supply of HBM4, which became the world’s first HBM4 to enter mass production and shipment in February. In December last year, Samsung’s HBM4 received top-tier evaluation after demonstrating an industry-leading 11.7Gbps speed in System-in-Package (SiP) testing, the final certification stage, the company adds.  According to News1, the latest development makes Samsung the first to supply HBM4E. Industry observers cited by the report also noted that starting from HBM4, customer-specific design flexibility and stable large-scale supply capabilities will become even more critical. Against this backdrop, Samsung’s integrated strengths across memory, foundry, and advanced packaging are expected to stand out even more clearly, the report adds.  HBM4E Upgrade with 20% Performance Boost, 30% Higher Capacity  In terms of performance, Samsung notes that HBM4E marks a notable upgrade over the previous generation, offering a stable 14Gbps pin speed that can scale up to 16Gbps for more demanding AI workloads. Compared with HBM4, the new memory delivers over 20% higher performance and reaches bandwidth of up to 3.6TB/s per stack, significantly improving compute efficiency for large language models (LLMs) and next-generation AI systems.  Additionally, Samsung’s 12-layer HBM4E is currently offered in a 48GB capacity, which is more than 30% higher than the previous generation. The company plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) variants to better align with diverse customer requirements as well.  From an efficiency standpoint, Samsung highlights that advanced low-power design techniques and an optimized packaging architecture have improved energy efficiency by 16% while reducing thermal resistance by more than 14% compared with the previous generation.  HBM4E Progress Among Rivals  Meanwhile, progress from SK hynix and Micron in HBM4E has come under closer market scrutiny following Samsung’s advances. According to Yonhap News Agency, SK hynix had initially planned to begin HBM4E sample shipments in the second half of this year, but recent reports indicate smoother-than-expected development progress, bringing forward its timeline.  On the other hand, Micron said its first HBM4E product will follow JEDEC standards, with mass production ramp-up targeted for 2027, according to STOCK Analysis.
2026-05-29 10:18 阅读量:336
Samsung Reportedly Develops Mobile HBM Packaging With Copper Pillars, Bandwidth Up 15%–30%
  Samsung Electronics is reportedly developing a next-generation HBM packaging technology aimed at bringing high-performance on-device AI to mobile devices. According to ETNews, sources say the company is working on a “Multi Stacked FOWLP” technology that combines ultra-high-aspect-ratio copper pillars with FOWLP (Fan-Out Wafer Level Packaging) by advancing its existing VCS (Vertical Cu-post Stack) technology.  The report notes that traditional mobile memory (LPDDR) packaging still relies on copper wire bonding. However, the technology is limited to roughly 128 to 256 I/O terminals, while also suffering from higher signal loss and lower thermal and power efficiency. To address these constraints, Samsung previously introduced its VCS (Vertical Cu-post Stack) technology, which arranges DRAM dies in a staircase-style stacked structure connected by copper pillars. The newly reported technology is viewed as a further evolution of this approach through the adoption of ultra-high-aspect-ratio copper pillars.  More specifically, Samsung has increased the aspect ratio of copper pillars used in VCS packaging from 3–5:1 to 15–20:1, significantly boosting bandwidth, the report notes. However, copper pillars thinner than 10 micrometers become more vulnerable to bending and breakage. To address this issue, Samsung reportedly combined the design with an FOWLP process, which molds the chip and extends wiring outward to help support the copper pillars.  The approach could enable more I/O terminals within the same area, potentially boosting bandwidth by 15% to 30% while increasing memory stack capacity by more than 1.5 times, the report adds.  Commercialization Timeline Remains Unclear  Meanwhile, the technology is still under development, making the timeline for mass production and commercialization unclear. However, the report says industry observers believe it could be adopted as early as a later version of the Exynos 2800 or the Exynos 2900.  Notably, some industry observers said mobile HBM development and commercialization could progress more slowly than initially expected, as demand for HBM in servers, data centers, and AI accelerators is expected to remain strong for the foreseeable future. The report adds that booming demand for server and data center HBM may make it difficult for Samsung to fully concentrate its resources on mobile HBM development.  SK hynix Advances Mobile AI Packaging  SK hynix is also accelerating development of semiconductor packaging technologies for smartphones and Extended Reality (XR) devices. According to a Hankyung report published earlier this year, sources say the company is developing “High Bandwidth Storage (HBS),” a packaging solution that vertically stacks low-power (LPDDR) DRAM and NAND flash memory beside the Application Processor (AP), which handles core computing tasks in IT devices.  Hankyung notes that HBS adopts a packaging technology called “Vertical Fan-Out” (VFO). Unlike conventional wire bonding, which connects stacked memory and substrates with thin copper wires, VFO uses pillar-shaped interconnects to enable denser wiring and faster data transfer speeds, helping APs process rapidly growing AI-driven workloads.
2026-05-15 10:49 阅读量:694
[News] Samsung Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed
  According to TechNews’ report, TSMC and Samsung fiercely compete in the semiconductor foundry sector. Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 mobile processor might adopt a dual-foundry strategy with TSMC and Samsung manufacturing simultaneously.  However, according to the latest industry information, due to Samsung’s conservative expansion plan for next year’s 3nm production capacity and unstable yields, Qualcomm has officially canceled the plan to utilize Samsung for next year’s processors. The dual-sourcing model is now postponed until 2025.  Samsung began mass production of its first-generation 3nm GAA (SF3E) process at the end of June last year, marking Samsung’s initial use of the innovative GAA architecture for transistor technology. The second-generation 3nm process, 3GAP (SF3), will utilize the second-generation MBCFET architecture, optimizing it based on the foundation of the first-generation 3nm SF3E. It is expected to enter mass production in 2024.  The dual-foundry strategy for Qualcomm was initially leaked by the reputable source Revegnus via the X platform (formerly Twitter). It was mentioned that the Snapdragon 8 Gen 4 processor would adopt TSMC’s 3nm (N3E) process, while Samsung’s 3GAP process would be used for the Snapdragon 8 Gen 4 supplying Samsung’s Galaxy series smartphones. Other sources suggested that due to limited capacity at TSMC’s 3nm production, Qualcomm had to seek Samsung as an alternative chip foundry.  As a result, Qualcomm originally anticipated dual-foundry production with both TSMC and Samsung in 2024, with hopes of being the first customer for the 3GAP process. However, considering Samsung’s conservative 3nm production capacity plan for next year and the instability in yields, Qualcomm decided to scrap the plan and exclusively rely on TSMC, pushing the dual-foundry strategy to 2025.  Currently, TSMC’s 3nm process technology capacity is on the rise, with expectations that by the end of 2024, monthly production capacity will reach 100,000 wafers, and the revenue contribution will increase from the current 5% to 10%.
2023-12-01 14:48 阅读量:4046
Samsung cuts NAND flash memory production
  • 一周热料
  • 紧缺物料秒杀
型号 品牌 询价
TL431ACLPR Texas Instruments
BD71847AMWV-E2 ROHM Semiconductor
RB751G-40T2R ROHM Semiconductor
CDZVT2R20B ROHM Semiconductor
MC33074DR2G onsemi
型号 品牌 抢购
ESR03EZPJ151 ROHM Semiconductor
TPS63050YFFR Texas Instruments
STM32F429IGT6 STMicroelectronics
BP3621 ROHM Semiconductor
IPZ40N04S5L4R8ATMA1 Infineon Technologies
BU33JA2MNVX-CTL ROHM Semiconductor
热门标签
ROHM
Aavid
Averlogic
开发板
SUSUMU
NXP
PCB
传感器
半导体
相关百科
关于我们
AMEYA360微信服务号 AMEYA360微信服务号
AMEYA360商城(www.ameya360.com)上线于2011年,现 有超过3500家优质供应商,收录600万种产品型号数据,100 多万种元器件库存可供选购,产品覆盖MCU+存储器+电源芯 片+IGBT+MOS管+运放+射频蓝牙+传感器+电阻电容电感+ 连接器等多个领域,平台主营业务涵盖电子元器件现货销售、 BOM配单及提供产品配套资料等,为广大客户提供一站式购 销服务。

请输入下方图片中的验证码:

验证码