<span style='color:red'>SiFive</span> announces first open-source RISC-V-based SoC platform with NVIDIA Deep Learning Accelerator technology
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SiFive announces first open-source RISC-V-based SoC platform with NVIDIA Deep Learning Accelerator technology

SiFive, a provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA’s Deep Learning Accelerator (NVDLA) technology.The demo will be shown this week at the Hot Chips conference and consists of NVDLA running on an FPGA connected via ChipLink to SiFive’s HiFive Unleashed board powered by the Freedom U540, the world’s first Linux-capable RISC-V processor. The complete SiFive implementation is well suited for intelligence at the edge, where high-performance with improved power and area profiles are crucial. SiFive’s silicon design capabilities and innovative business model enables a simplified path to building custom silicon on the RISC-V architecture with NVDLA.NVIDIA open-sourced its leading deep learning accelerator over a year ago to spark the creation of more AI silicon solutions. Open-source architectures such as NVDLA and RISC-V are essential building blocks of innovation for Big Data and AI solutions.“It is great to see open-source collaborations, where leading technologies such as NVDLA can make the way for more custom silicon to enhance the applications that require inference engines and accelerators,” said Yunsup Lee, co-founder and CTO, SiFive. “This is exactly how companies can extend the reach of their platforms.”“NVIDIA open sourced its NVDLA architecture to drive the adoption of AI,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. “Our collaboration with SiFive enables customized AI silicon solutions for emerging applications and markets where the combination of RISC-V and NVDLA will be very attractive.”
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Release time：2018-08-21 00:00 reading：1249 Continue reading>>
<span style='color:red'>SiFive</span> Preps RISC-V Cloud Service
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SiFive Preps RISC-V Cloud Service

　　SiFive will try to build an easier, cheaper, faster way to design chips with a new $50.6 million funding round that included Huami, the venture arm of China’s Xiaomi. The series C aims to bring the startup to profitability and establish a broad market for its RISC-V cores.　　SiFive will release a cloud service for designing RISC-V cores this year. It will expand it into an SoC design platform next year with silicon blocks from partners, said Naveed Sherwani, an industry veteran named chief executive of SiFive last July after 10 years at Open Silicon.　　At an event announcing the funding, Sherwani made several ambitious promises he said would amount to a revolution in SoC design.　　“Today it takes 9-18 months to finish a chip. In 12-18 months we will release a system that takes besides the two-month’s fab time, just 15-20 days… today people take 30 days to validate RTL, but we will do it in less than 3-5 hours — this is my promise,” he said.　　In addition, SiFive’s IP partners will provide blocks at low or no cost until an SoC is in production. Upfront charges for IP can amount to 35 percent of the cost of prototyping an SoC, as much as $5 million in some cases. SiFive aims to reduce those costs as much as 85 percent so users can prototype a chip for roughly $750,000, said Shafy Eltoukhy, who oversees SiFive’s partner program.　　“Anyone with a Web interface will be able to design amazing chips and solve problems in their communities,” said Sherwani, vowing to make the service free for universities and developing countries.　　Some of SiFive’s promises are “very ambitious,” said market watcher Linley Gwennap of the Linley Group. Speeding up the design process is good, but it doesn’t add differentiation, “so the value of this approach is unclear. Most SoC startups design the most crucial IP blocks on their chips to ensure differentiation,” he said.　　Although SiFive may reduce upfront costs, “customers still have to pay for the IP later when they ship product, so the program doesn’t reduce IP cost, it just delays it,” he added.　　It’s not yet clear where SiFive’s platform will get traction. The service could give the emerging class of crowdfunded hardware startups an alternative to using off-the-shelf chips. Existing chip designers might find the service useful in lowering costs for SoCs that don’t require custom features.　　To date, a handful of established electronics companies such as Microsemi, Nvidia and Western Digital are adopting RISC-V. They see the free instruction set architecture and its growing set of open source implementations as a way to reduce costs of designing their own cores.　　Startup Esperanto Technologies announced last fall it is developing a family of high-end processors with RISC-V. And Andes Technology is embracing RISC-V as an alternative to its proprietary cores.　　The new funding round was a large one for SiFive. The company,founded in July 2016 by a team of Berkeley grad students and their advisor who designed the initial RISC-V cores, had raised $13.8 million to date.　　Investors were led in the latest round by Chenwei, a China VC firm with a broad tech portfolio that includes investments with Sutter Hill Ventures, SiFve’s initial lead investor. Other new investors included SK Telecom, Huami, two unnamed semiconductor companies and Western Digital, an existing RISC-V user.　　“A lot of the RISC-V revolution will happen in China and India,” said Stefan Dyckerhoff, a managing director at Sutter Hill Ventures.　　Sherwani said the funds will help him double his team to about 100 people, hiring mainly engineers with a combination of silicon and software expertise. It will also pay for about a dozen tape outs he wants to do this year to verify partner IP.　　The SiFive cloud service he aims to build will let users create SoCs by selecting pre-verified RISC-V cores and peripheral IP blocks. It will generate fab-ready files, generally shielding customers from the complex details of EDA flows.　　The service also will support an app store of tools from SiFive and its partners. A basic version of the service for designing RISC-V cores could be available as early as September.　　SiFive’s IP partner program, launched in August, includes a dozen generally small IP companies so far and is adding a new member about every two weeks.　　They include Analog Bits, Dover Microsystems, FlexLogix, Rambus and UltraSoC. DSPs are among the holes it has yet to fill.　　Much of SiFive’s work behind the scenes will be in creating templates for each block, building subsystems of multiple blocks and making sure each combination of blocks can work together.　　Meanwhile the company is already logging revenues from licenses for a handful of RISC-V cores it has designed to date. SiFive’s first purchase order was issued in mid-2016 for a soft core that acts as a cache coherent block in a Microsemi design.　　“This week we received a multimillion-dollar order for the program that uses that processor from SiFive,” said Ted Speers, a Microsemi fellow and a board member of the RISC-V Foundation.　　Some see RISC-V upending the dominance of Intel and Arm in microprocessors. At a RISC-V event last fall, WD said it will standardize on RISC-V and someday ship as many as two billion cores a year embedded in its disk and solid-state drives.　　“Based on how Linux went from enthusiast users to a major OS for the data center, I predict in 10 years we will see every data center processor and half of edge device processors use RISC-V. All the control points will be broken, so you can build an SoC any way you want, with any interfaces you want— this is the freedom RISC-V will bring by 2028,” said Zvonimir Bandic, a senior director at WD and a board member of the RISC-V Foundation.　　“I’m concerned that the talk of RISC-V eventually dominating the data center and client computing distracts from the hard work that needs to be done in the interim,” said analyst Gwennap. “So far, RISC-V has been adopted only for deeply embedded cores and not for running application software,” he added.　　While others such as Esperanto will go head-to-head with giants such as Intel, that is clearly not SiFive’s goal.　　Some developers have been keen to get their hands on SiFive’s latest processor, because it is the first RISC-V chip capable of running Linux. At the event last week, the company did not even mention it had just shipped a few cases worth of developer cards with the chips.
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Release time：2018-04-03 00:00 reading：1146 Continue reading>>
RISC-V Boots Linux at <span style='color:red'>SiFive</span>
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RISC-V Boots Linux at SiFive

　　SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.　　A single 64-bit U54 core delivers 1.7 DMIPS/MHz or 2.75 CoreMark/MHz at 1.5 GHz. It measures 0.234 mm2 including its integrated 32+32KB L1 cache in a TSMC 28HPC process using a 12-track library.　　A quad-core complex with a 2-MByte shared coherent L2 cache, Gbit Ethernet and DDR3/4 controllers and other peripherals measures ~30 mm2. SiFive will deliver a quad-core chip that includes an E51 management core that will ship in the first quarter on boards targeting software developers.　　The single-issue, in-order U54 is expected to lag the performance of ARM’s dual-issue A53. By comparison, in late 2014 Freescale (now NXP) announced the QorIQ LS1043A, a midrange quad-core A53 running at 1.5 GHz delivering more than 16,000 CoreMarks at 6 W.　　SiFive believes its part will be competitive in power and area efficiency. It also aims to innovate in its business model.　　The startup will offer designers 100 prototype SoCs for $100,000 with no fees on third-party IP bundled with its cores until customers ship their chips. “Today, you pay all the IP costs upfront — we think that’s the wrong way,” said Jack Kang, vice president of business development for SiFive.　　It’s still early days for RISC-V vendors and users.　　Microsemi and Arduino are SiFive’s only announced customers. The startup claims that it already has multiple licensees of the U54, including military contractors and large semiconductor companies that serve markets including set-top boxes and data center accelerators.　　Its existing 32- and 64-bit embedded cores have multiple licensees in areas including wearables and storage controllers. Several large chip makers are still evaluating RISC-V for potential use in multiple projects, said Kang.　　For its part, Microsemi uses RISC-V as the PolarFire soft core in its FPGAs. The open source ISA offers lower cost and greater trust given its inspectable RTL, said Bruce Weyer, vice president of Microsemi’s programmable solutions group. He believes those advantages and others will help RISC-V proliferate, but it will take time.　　“We’ve seen rapid adoption of RISC-V in MCUs but there’s a different maturity level in Linux,” Weyer said.　　Processor IP vendors Andes and Cortus announced plans for RISC-V compliant cores earlier this year. The relatively small players are expected to eventually transition to the open-source architecture.　　“It’s hard to put your finger on big market success for RISC-V yet because it’s too early to see SoC and systems shipments,” said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, California).　　“SiFive is certainly making good progress, and with the U54, it can now go after a broader range of embedded designs. The previous products were limited to use with an RTOS or other microcontroller-like designs.”　　As for vendor support, “there’s been a surprising amount of work on RISC-V Linux systems to date using simulators and emulators,” said Kang. “Getting silicon will help spur the software ecosystem.”　　UltraSoC recently joined Rambus as a member of SiFive’s third-party IP program called DesignShare, providing trace and debug tools and SoC monitors. SiFive aims to announce several more IP partners before the end of the year.　　Separately, engineers hope to define a vector version of the RISC-V instruction set by the end of the year, targeting applications such as machine learning. A hypervisor mode is also in the works to enable virtual machines on RISC-V.
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Release time：2017-10-10 00:00 reading：1188 Continue reading>>

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