<span style='color:red'>Rambus</span> acquires memory technology assets of Diablo Technologies
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Rambus acquires memory technology assets of Diablo Technologies

　　Rambus Inc. today announced it has acquired the assets of Diablo Technologies to broaden its portfolio in the hybrid DRAM and Flash memory markets. These patented innovations augment the existing Rambus NVDIMM portfolio and complement its high-bandwidth, low-power memory technologies. Specific terms of the deal are not disclosed.　　For over ten years, Diablo Technologies was a pioneer in the development of NVDIMM technologies for high-speed, low-power, and low-latency bridging and switching products targeted at the server and storage markets. Having developed memory buffer and software solutions leveraging an all-Flash memory sub-system, Diablo Technologies enabled an architecture to rewrite the rules of data center performance and economics. Rambus’ investment in these technology areas provide a foundation for integrating existing DRAM and Flash along with emerging memories into advanced hybrid memory systems in the future.　　Expanding emerging memory technology for high memory bandwidth interfaces is key to Rambus’ strategic core business. The company has also been collaborating with IBM to research hybrid memory systems, as announced previously.　　“Adding these breakthrough innovations from Diablo Technologies will continue to grow Rambus’ leadership in non-volatile and hybrid DRAM and Flash memory technologies with foundational patents,” said Kit Rodgers, SVP of Technology Partnerships and Corporate Development, Rambus. “Diablo Technology’s patented innovations were ahead of their time and nicely complement our offerings for existing and new customers.”
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Release time：2019-01-18 00:00 reading：1033 Continue reading>>
<span style='color:red'>Rambus</span> Taps RISC-V for Root of Trust
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Rambus Taps RISC-V for Root of Trust

　　Rambus announced a security block based on the RISC-V core aimed, in part, to plug the Meltdown/Spectre flawsrevealed earlier this year. The CryptoManager Root of Trust targets use in a wide spectrum of ASICs, microcontrollers, and SoCs in embedded systems.　　Rambus claims that the new block sports several advantages over root-of-trust functions already integrated in most existing embedded processors. It suggested that OEMs should move this fundamental hardware-security function out of mainstream x86 and ARM embedded processors that Spectre/Meltdown showed are vulnerable to side-channel attacks.　　However, an NXP security expert said that the root-of-trust function ideally should be implemented in a standalone chip, a practice that high-security systems use. The trend of integrating the function into larger chips helped save costs, but it was a step backward in security, said Sami Nassar, vice president of cybersecurity solutions at NXP Semiconductors.　　“The security execution environment and the root of trust should be outside the main processor … you don’t want to mix security and general processing,” he said. “It’s not complicated to [isolate the two], and it doesn’t add much cost, but people cut corners, and it’s proven to be a weak model.”　　Rambus argues that its block lets designers at least move the key security functions off of embedded processors that often use speculative execution. Spectre/Meltdown showed that the popular performance-boosting function can leave secure data exposed in caches.　　Nassar countered that highly secure systems generally use standalone root-of-trust chips separately from host processors. Integrated chips are more vulnerable because they share I/O and cache blocks, he said.　　The first mainstream implementations of hardware root-of-trust security defined by the Trusted Computing Group nearly 15 years ago were standalone chips called secure modules. However, over time, major processor and IP vendors such as Intel and ARM subsumed those functions in their chips.　　The big processor and IP vendors argued that their implementations kept secure and open paths separate inside a chip. However, the Spectre/Meltdown attacks showed that the complexity of today’s devices leave room for vulnerabilities that are sometimes not found for years.　　Rambus and others argue that the new block and the RISC-V core that it is based on have advantages over transitional implementations of a root of trust.　　For example, the CryptoManager supports multiple roots, letting processes use the core without exposing keys or secrets to other processes. The Rambus core is fully programmable and sports new levels of protection against side-channel attacks, emulation, reverse-engineering, and other hacks.　　A Rambus security expert was one of the researchers behind the initial papers on Spectre/Meltdown. The company announced last year that it would adopt a RISC-V core from startup SiFive for use in security applications.　　After some initial hiccups, Intel said in March that it now has firmware available to mitigate Spectre/Meltdown flaws in its processors as much as nine years old. It promised that changes in hardware to plug the flaws will emerge in new Xeon and Core chips starting in the second half of this year.　　“The semiconductor industry faced some of its biggest security issues this year with recent vulnerabilities, and the potential to encounter additional security flaws will not go away any time soon as more IoT devices enter the market,” said Abhi Dugar, an IoT security analyst for International Data Corp., speaking in a Rambus press release.　　“To address existing and new threats, establishing trust at the hardware level will be critical, and a secure siloed core can help ensure that this new generation of devices can be protected from security flaws.”
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Release time：2018-04-17 00:00 reading：1195 Continue reading>>
DDR5 Runs in <span style='color:red'>Rambus</span>’ Labs
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DDR5 Runs in Rambus’ Labs

　　Rambus has working silicon in its labs for DDR5, the next major interface for DRAM dual in-line memory modules (DIMMs). The register clock drivers and data buffers could help double the throughput of main memory in servers, probably starting in 2019 — and they are already sparking a debate about the future of computing.　　The Jedec standards group plans to release before June the DDR5 spec as the default memory interface for next-generation servers. However, some analysts note it comes at a time of emerging alternatives in persistent memories, new computer architectures and chip stacks.　　“To the best of our knowledge, we are the first to have functional DDR5 DIMM chip sets in the lab. We are expecting production in 2019, and we want to be first to market to help partners bring up the technology,” said Hemant Dhulla, a vice president of product marketing for Rambus.　　DDR5 is expected to support data rates up to 6.4 Gbits/second delivering 51.2 GBytes/s max, up from 3.2 Gbits and 25.6 GBytes/s for today’s DDR4. The new version will push the 64-bit link down to 1.1V and burst lengths to 16 bits from 1.2V and 8 bits. In addition, DDR5 lets voltage regulators ride on the memory card rather than the motherboard.　　In parallel, CPU vendors are expected to expand the number of DDR channels on their processors from 12 to 16. That could drive main memory sizes to 128 Gbytes from 64 GB today.　　DDR5 is expected to first appear on high performance systems running large databases or memory-hungry applications such as machine learning. While some servers may lag adopting DDR5 for six months or so, “it’s just a couple quarters, not a couple years…Everyone wants a fatter memory pipe,” said Dhulla.　　About 90 percent of today’s servers use registered or load-reduced DIMMs that employ register clock drivers and data buffers. The chips generally are sold for less than $5 by companies including Rambus, IDT and Montage.　　The DDR5 standard will arrive about the same time Jedec releases its NVMDIMM-p interface for memory modules supporting a mix of DRAM and persistent memory. Intel said it will roll out server DIMMs next year using its 3D XPoint chips. Others are expected to ship NVMDIMM-p cards using 3D NAND.　　The new cards are expected to eke out advantages in density and latency compared to traditional DRAM modules. However, they are expected to carry higher prices, and DRAMs are expected to maintain a raw speed advantage.　　DDR5 “is much needed…but it still DRAM and still power hungry. It drives the traditional Von Neuman systems, but we still need to come up with persistent memory alternatives and new computing models,” said Alan Niebel, president of market watcher WebFeet Research.　　Indeed, last year Hewlett-Packard Enterprise unveiled a prototype system using the GenZ memory interface that had a coming out party in August.　　A lot of people don’t think DDR5 will be the next-generation memory interface,” said Gil Russell, a principal analyst at WebFeet.　　Process technology shrinks for DRAMs are approaching the physical limits of its core capacitors, leading some such as Russell to project the end the memory designs in five to ten years. Higher error rates are already requiring correcting code circuitry on the chips, he noted.　　The memory card sector, however, “is an area that moves really slowly. It takes a year just to get DIMMs qualified, and they are wanted at the lowest possible cost,” said Russell.　　Meanwhile, high-end graphics processors from AMD and Nvidiahave already moved to High Bandwidth Memory chip stacks to boost speed and density. Dhulla of Rambus noted chip stacks are still an expensive approach limited to high-end GPUs, FPGAs and communications ASICs　　“DDR5 is clearly the path to a high-volume opportunity. The big industry debate is what happens beyond DDR5, beyond 2023. Our labs are looking at multiple alternatives,” said Dhulla.
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Release time：2017-09-21 00:00 reading：1095 Continue reading>>
<span style='color:red'>Rambus</span> Adds Security to RISC-V
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Rambus Adds Security to RISC-V

　　Startup SiFive announced a new program providing third-party intellectual property blocks for its RISC-V processors. Its first partnership is for security hardware from Rambus.　　Rambus will provide a crypto core optimized to connect to its IoT device management services and run on the SiFive Freedom chips. The Rambus core enables a secure connection, attestation and device monitoring, said Martin Scott, general manager of Rambus’s security group.　　The core is the first member of what SiFive calls DesignShare. “SiFive welcomes everybody to join DesignShare — Rambus is the first of many partners we will be announcing soon,” said Jack Kang, vice president of product and business development at the startup.　　The program aims to deliver IP “at a low or reduced up front cost,” he said. The blocks will not necessarily be based on open source code.　　SiFive officially launched in May its first two cores available on its Web site. Although the RISC-V instruction set is open source, the cores require a one-time licensing fee. SiFive does not charge per-unit royalties.　　SiFive CTO and co-founder Yunsup Lee will give a talk at Hot Chips this week about the company’s products first announced in 2016 as well as the Rambus partnership.　　Earlier this month, SiFive named industry veteran Naveed Sherwani its CEO. Sherwani has helped found nine startups to date including Open Silicon and Brite Semiconductor. He also helped pioneer Intel’s move to a more open EDA platform for its first ASIC service.
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Release time：2017-08-22 00:00 reading：1206 Continue reading>>
<span style='color:red'>Rambus</span> Reportedly Exploring Sale Possibilities
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Rambus Reportedly Exploring Sale Possibilities

　　Memory technology licensor and chip vendor Rambus Inc. is working with a financial advisor to study options for its sale, according to a report by the Bloomberg news service.　　No final decisions have been made about selling the company, according to the report, which cites anonymous sources.　　Rambus declined to comment on the report through a spokesperson.　　Rambus is a Sunnyvale, Calif.-based company with a long history of patent litigation, including successful litigations against many of the largest memory chip vendors in the late 2000s. After years of collecting significant royalties from its double data rate (DDR) technology and earning a reputation as a patent troll, Rambus, which claims more than 2,500 technology patents returned to its roots as a fabless chip vendor in 2015.　　After two years of unprecedented merger and acquisition activity, consolidation in the semiconductor industry has cooled in 2017. Imagination Technologies plc, a fellow IP licensor, is also exploring the sale of the company in light of losing its top customer, Apple, earlier this year.
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Release time：2017-07-11 00:00 reading：1057 Continue reading>>
<span style='color:red'>Rambus</span>, Microsoft Heat Up With Cold DRAM
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Rambus, Microsoft Heat Up With Cold DRAM

　　A community of computer scientists striving to respond to soaring system demand for real-time data processing has just received some good news.　　Rambus revealed Monday (April 17) that the company, in collaboration with Microsoft researchers, will have an early prototype of cryogenic memory in a month, and a more complete one by the end of the year. The new technologies will be essential to data centers, “currently the fastest growing consumer of memory” in the industry, Craig Hampel, chief scientist at Rambus, told EE Times.　　The new memory subsystems will be able to operate below minus?180 °C or minus?292.00 °F or 93.15 kelvin. This will substantially reduce energy consumption and improve the overall performance of a bank of computers deployed in the cloud for massive data processing, he explained.　　Rambus and Microsoft struck a deal in late December, 2015 to pool resources and develop memory systems for next-generation quantum computing.　　Rambus’ announcement on Monday is the first tangible result of the joint efforts. Such cryogenic techniques mark a significant change in DRAM operating temperatures.　　However, during the initial partnership announcement, the two companies did not mention the development of cryogenic DRAM. Instead, they appeared more interested in developing memory systems for next-generation quantum computing. So, how does their latest announcement relate to that?　　Hampel explained that this all fits into a greater strategy to advance systems to superconducting computing and ultimately to quantum computing. Rambus explained that by breaking down the cryogenic systems’ long-term goal for quantum computing in bite size, they have applied the new technologies to prototyping DRAM that can operate below 90 kelvin.　　The U.S. National Institute of Standards and Technology has chosen to consider the field of cryogenics as that involving temperatures below minus?180 °C or minus?292.00 °F or 93.15 kelvin (K).　　Conventional DRAM operates at room temperature – roughly at 350 and 350 K. By cooling down to 90 K, “you bring down the leakage to zero, while achieving higher performance at a much lower temperature,” explained Hampel.　　Once you bring the temperature down to 7 K, that’s when you get into the superconducting domain, he added. “It allows all of the interconnect power to become zero.”　　To get to quantum computing, however, cryogenic memory must “operate at 20 to 40 millikelvin, which is essentially colder than deep space,” said Hampel.　　Thus far, by succeeding in a DRAM prototype that works at colder than 90 K, Rambus is “hopeful,” said Hampel, that this leads to “better DRAM scaling, lowering cost and increasing reliability” in subsystems currently under tremendous thermal stress.　　The goal is a cryogenic memory subsystem in the next two to three years, according to Hampel.　　To get there, the Rambus-Microsoft partnership is still missing a third leg: DRAM and foundry suppliers. Rambus isn’t announcing that today but will soon need to address it.　　In search of new memory architecture　　Looking back on Rambus’ history, Hampel said, “We have always pushed the new memory architecture” in new markets. In the late ’80s to early ’90s, Rambus went after the PC market with its proprietary memory technologies, and ended up entangled in a standards war. Then, by mid-1990s, Rambus shifted focus to the video game console market, getting its RDRAM adopted by Nitendo 64 and Sony’s PlayStation.　　As the growth of PCs and game consoles have slowed and smartphones are getting fragmented, Hampel said, “We approached Microsoft for partnership,” as both companies identified data centers as “the best home for new memory innovation.”
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Release time：2017-04-17 00:00 reading：1072 Continue reading>>

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