<span style='color:red'>ISSCC</span> Keynotes Call for Creativity
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ISSCC Keynotes Call for Creativity

　　SAN FRANCISCO — Executives and technologists put a positive spin on the increasing cost and complexity of scaling semiconductors in opening talks at the International Solid-State Circuits Conference here. They rallied several hundred chip designers at this annual gathering to think out-of-the-box.　　“The ending of Moore’s law and Denard scaling means new innovations are needed in instruction set architectures… I think we are entering another renaissance in computer architecture,” said David A. Paterson, professor emeritus at the University of California-Berkeley, noting venture capitalists spent as much as $1.5 billion on chip startups last year.　　“The incoming class of PhD candidates is the best we can remember, and undergrads are getting excited about designing hardware again — neural networks a big part of it,” he said, citing the Tensorflow Processor Unit he contributed to at Google and the RISC-V architecture he helped launch.　　“Moore’s law has been in some ways shackles leading us to multimillion dollar masks and multibillion dollar wafer fabs… the Moore’s law era was relatively constrained, the future was calibrated…now we can get off that path, look around and really do some interesting things together,” said Vince Roche, chief executive of Analog Devices Inc. (ADI), in his keynote.　　Roche called for applications-led innovations across multiple dimensions including materials, packaging and software. He described three ADI products as examples.　　ADI’s chip-scale pH sensor combines semiconductor processes such as electroplating, wafer bonding and microfludic channels. The micro-module packaging of Linear Technologies, now part of ADI, handles 100A power loads that required ten modules a decade ago. In addition, ADI combines analytics and signal processing in a smart power meter to detect and reduce a $96 billion/year problem utilities face with power theft.　　“We invest in chemists, cryptographers and even physicians to a fuller understanding of applications and market,” he said.　　For his part, Patterson noted the RISC-V Foundation has now attracted more than 100 members supporting the open instruction set architecture.　　“I can’t believe RISC still the best idea in processor architecture, but it is,” he said in brief overview of the last 50 years of computing. “Our modest goal is to become world dominating and be the ISA you run every day,” he quipped.
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Release time：2018-02-13 00:00 reading：1287 Continue reading>>
Samsung Shows EUV Design at <span style='color:red'>ISSCC</span>
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Samsung Shows EUV Design at ISSCC

　　Samsung will describe a 7nm SRAM made with extreme ultraviolet lithography (EUV) at the International Solid-State Circuits Conference in February. Other ISSCC papers will detail memories, sensors and processors spanning everything from fast DRAMs to location trackers embedded in a boot.　　Reinforcing its commitment earlier this year to be the first chip maker to use EUV, Samsung will describe a 0.026μm2 SRAM bit cell in a 7nm process it aims to make available next year. The chip is the smallest SRAM described to date and uses a double-write driver to reduce minimum supply voltage.　　Two papers on specialty memories should attract attention. TSMC will describe an 11 Mbit resistive RAM macro made in a 40nm process. It uses a new sense amplifier TSMC claims offers a 58 percent faster access speed as well as a new write scheme to improve endurance and retention.　　Separately, Japan’s Semiconductor Energy Laboratory will discuss a 60nm crystalline oxide semiconductor FET used in a deep-learning accelerator due to its speed and low power. The Kbit cell can be read in 45ns and written in 20ns, drawing 97.9pJ and 123pJ of energy.　　Papers in more conventional DRAM and flash sessions show stepwise advances with few surprises.　　Samsung and SK Hynix will describe 16 and 8 Gbit GDDR6 DRAMs, respectively, with maximum data rates of 16-18Gbits/s/pin using single-ended signaling. SK Hynix also will detail its eight-layer HBM2 that delivers 64 Gbits of memory on a 341 GByte/s interconnect.　　In flash, Samsung will present its much-discussed Tbit NAND based on 64 stacked layers and four bits/cell. Toshiba and Western Digital will counter with a 512 Gbit design using three bits/cell in a 96-layer stack. Separately, Samsung will describe its Z-NAND that achieves a 15μs latency as well as a solid-state drive controller for it that aims to compete with Intel’s Optane drives.　　ISSCC typically packs a few papers from the left field of silicon research. This year’s event sports at least two in sensors.　　A group of researchers from four universities will present a smart shoe that helps walkers find their way when GPS signals are not available. It combines a MEMS sensor array, a low-power interface ASIC and a nine-axis inertial measurement unit embedded in the heel of a boot to deliver position accuracy of 5.5 meters over a 3.1 km distance.　　Separately, researchers from South Korea will show how they packed a 360-degree camera into an ingestible capsule. They used four cameras and a set of distributed “body-channel” transceivers to create an 80Mbit/s link to the capsule that delivers four frames/s at VGA resolution and can locate the capsule to within less than a centimeter.　　Session organizers said it marks the first such device with wireless telemetry. It “increases the patient’s autonomy and reduces health care costs significantly by facilitating cloud-based remote patient monitoring,” they added.　　In more conventional sensors, Sony and Microsoft will push the limits of CMOS imagers and time-of-flight cameras.　　Sony will describe a 1.46MP BSI global shutter CMOS image sensor expected to be used for scientific and industrial applications. It employs an in-pixel ADC thanks to 3D stacking techniques that Sony’s imagers continue to pioneer.　　For its part, Microsoft will present a 1024×1024 time-of-flight image sensor made in a TSMC 65nm process. Organizers said it sports the smallest pixels and highest resolution for such products routinely used in gaming, virtual reality, augmented reality and the Internet of Things.　　Interestingly, TSMC will show a new architecture for a CMOS imager aimed to increase video frame rates four- to nine-fold. The 13.5MP 3D-stacked sensor uses a bank of column ADCs, and is likely a showcase of the company’s CMOS imager process.　　In what will likely be one of the more heavily attended sessions at ISSCC, Google will present the concept of a single compute fabric for machine-learning from the device to the data center as well as the technical challenges to enable it. To date, Google has been relatively forthcoming about its TPU accelerator for the data center,but has said less about client hardware.　　Separately, David Patterson, a retired Berkeley professor and author now working at Google on the TPU and other projects, will give a keynote on the history of computer architectures. Many other papers will describe machine-learning accelerators, but they are generally academic efforts.　　Processor papers in the ISSCC advance program held few surprises. For example, Intel will detail its Skylake server CPU released earlier this year, IBM will discuss its previously announcedz14 mainframe host and AMD will present more information on how it packaged its multichip Zen x86 processors.　　One interesting paper from Intel is probably a research effort. It details a 14nm centimeter-scale self-powered IoT edge node with a 25 mW peak power consumption. It runs at 200-950 MHz and packs an x86 core, blocks to process crypto operations and convolutional neural nets, a “sub-mW wake-up radio” and 512KB memory.　　In a session on wired communications, Intel and IBM will both describe state-of-the-art 112 Gbit/s serdes using PAM-4 modulation. STMicroelectronics will present a 56G serdes made in an FD-SOI process.
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Release time：2017-11-14 00:00 reading：1419 Continue reading>>

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