EU Consortium Targets Exascale Computing SoC

　　Following three successive Mont-Blanc projects since 2011, the three core partners Arm, Barcelona Supercomputing Center and Bull (Atos Group) have come together to develop the next generation of industrial processor for high performance computing (HPC). The latest project is looking to pave the way to a future low-power European processor and ecosystem for exascale computing systems, with new European Commission Horizon2020 funding of 10.1 million Euros (about $12 million).

　　The Mont-Blanc 2020 consortium also includes CEA, Forschungszentrum Jülich, Kalray and SemiDynamics.

　　The Mont-Blanc project vision is to leverage mobile technology for scientific computation. Its goal was to initiate a family of processors that will be the basis of HPC exascale systems that can achieve market adoption and economic sustainability.

　　The aim of the first project in 2011 was to produce a new type of computer architecture capable of setting future global HPC standards that will provide exascale performance using 15 to 30 times less energy. From 2013 to 2016, the extension of Mont-Blanc was aimed at developing extreme scale energy-efficient platforms, with potential for exascale computing, addressing the challenges of massive parallelism, heterogeneous computing and resiliency.

　　The third phase of the Mont-Blanc project, running from 2015 to 2018, aimed to build upon the previous Mont-Blanc & Mont-Blanc 2 projects. Its co-design approach is intended to ensure that hardware and system innovations are readily translated into benefits for HPC applications.

　　The latest funding is the fourth iteration of the project, aiming to improve the economic sustainability of the processor generations that will result from the Mont-Blanc 2020 effort. The project is based on modular packaging to enable the creation of a family of SoCs targeting different markets, such as "embedded HPC" for autonomous driving. The project’s objectives are to:

• define a low-power system-on-chip architecture targeting exascale;

• implement new critical building blocks (IPs) and provide a blueprint for its first-generation implementation;

• deliver initial proof-of-concept demonstration of its critical components on real life applications;

• explore the reuse of the building blocks to serve other markets than HPC, with methodologies enabling a better time-predictability, especially for mixed-critical applications where guaranteed execution and response times are crucial.

　　The project will have to tackle three key challenges to achieve the desired performance with its targeted power consumption:

• understand the trade-offs between vector length, NoC (network on chip) bandwidth and memory bandwidth to maximize processing unit efficiency;

• an innovative on-die interconnect that can deliver enough bandwidth to the processing units, with minimum energy consumption;

• a high-bandwidth and low power memory solution with enough capacity and bandwidth for exascale applications.

　　“The ambition of the consortium is to quickly industrialize our research. This is why we decided to rely on the Arm instruction set architecture, which is backed by a strong software ecosystem. By leveraging the current efforts, including the Mont-Blanc ecosystem and other international projects, we will benefit from the system software and applications required for successful usage,” explained Said Derradji, Atos, coordinator of the Mont-Blanc 2020 project.