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TSMC 3<span style='color:red'>-nm</span> Fab Environmental Assessment Approved, to Commence in 2020

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TSMC 3-nm Fab Environmental Assessment Approved, to Commence in 2020

Taiwan's Environmental Administration yesterday approved the environmental assessment for Taiwan Semiconductor Manufacturing Company, Limited's (TSMC) 3-nanometer factory, signifying that TSMC's 3-nm factory will be able to commence operations on schedule in 2020 with total investment amounting to NT $600 billion.The point of this environmental evaluation was concerns about water and electricity usage and whether or not they would bring about any impacts on the water usage of local residents. However, after Taipower and the Water Resources Agency guaranteed a completely flawless supply, the evaluation was amended and passed.Regarding this decision, TSMC stated that they have selected Southern Taiwan Science Park as the location to establish a 3-nm process factory to manufacture their 12-inch chips.Meanwhile, TSMC also pledged that after commencing mass production they will expand the use of renewable energy each year, and in order to reduce power consumption burdens in the local area, they expect to use renewable energy for 20% of overall consumption.

Key word：

TSMC

Release time：2018-12-21 00:00 reading：1298 Continue reading>>

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TSMC to Build a New 200mm Fab for Customized Design; 5-nm to Enter Trial Production Next Year

C.C. Wei, CEO and vice chairman of TSMC, said at its supply chain management forum held in Hsinchu, Taiwan, that TSMC's 5nm process is expected to enter trial production in the second quarter of next year. In addition, TSMC will establish a new 8-inch(200mm) fab to meet the requirements of the customized design.C.C. Wei said that TSMC's 5nm process is scheduled to enter trial production in the second quarter of next year, and will enter mass production in the second quarter of 2020. Furthermore, in order to meet customers' specific process, TSMC is planning to build a new 8-inch fab for customized design.Wei also stressed that the 5G and artificial intelligence (AI) will be the main growth momentum of the semiconductor industry. The 5G applications will be gradually deployed in the second half of 2019 to 2020, and AI will also be extended to edge computing from the cloud.With the help of these technology trends, TSMC forecasted that its revenue will grow by 5% to 10% in the next few years.

Key word：

TSMC

Release time：2018-12-10 00:00 reading：1147 Continue reading>>

Apple Describes 7<span style='color:red'>-nm</span> iPhone SoC

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Apple Describes 7-nm iPhone SoC

Apple announced a family of three iPhones powered by a 7-nm SoC enabling up to 512 GBytes of memory. The handsets range in price from $749 to $1,099, increase battery life by 30 to 90 minutes, and ship within two to six weeks.The smartphones, and two new models of the Apple Watch, generally packed larger screens and upgraded chips in slightly smaller devices. None of the devices support 5G cellular networks, expected to start switching on later this year, but the handsets support Gbit/s data rates, an LTE capability that Qualcomm was early to support.Apple’s 7-nm A12 Bionic chip packs 6.9 billion transistors and is “the most powerful chip in a smartphone,” said chief executive Tim Cook.The A12’s two high-performance CPU cores deliver 15% more speed and 40% greater efficiency than the prior A11. Four other cores are 50% more efficient than those on the prior chip. The 10-nm A11 was touted as sporting up to 25% more performance and 70% more efficiency than its predecessor, reinforcing reports that the 7-nm node delivers declining advantages.The A12 packs a six-core GPU designed by Apple, said to be 50% faster than the block on the A11. An upgraded neural engine sports eight cores, up from two in the A11. Apple claims that it delivers a nine-fold performance gain on its CoreML machine-learning framework, hitting 5 trillion operations/s, up from 600 billion ops/s on the A11 using one-tenth of the energy.The performance will speed a variety of operations, including unlocking the phone using Apple’s facial-recognition software. It also enables a new capability to group multiple Siri functions into shortcuts.Third-party developers showed applications using Apple’s CoreML and ARKit 2 frameworks to enable new features supported by neural nets. They included Homecourt, an app tracking six metrics of basketball performance in real time, as well as new features in mobile games using augmented reality.“The A12 is a game changer,” said Tim Bajarin, a veteran Apple watcher and president of Creative Strategies. “Five billion transactions per second will drive more powerful neural network and AI functions, making these new iPhones the most powerful smartphones on the market.”The new handsets use 6.5- and 5.8-inch OLED displays supporting 458 pixels/inch and a 6.1-inch LCD on a low-end model supporting 326 pixels/inch. The iPhone XS and XS Max include dual 12-Mpixel-wide and telephoto cameras while the low-end XR uses a single 12-Mpixel camera.All of the cameras support a variety of features, including HDR10 and adjustable depth-of-field, relying on an image processor and the neural engine in the A12. “This is a new era of computational photography,” said Phil Schiller, Apple’s vice president of marketing.Apple wound up the performance of its smartwatch with an S4 system-in-package using two 64-bit CPU cores to deliver twice the performance of its existing devices. The Apple Watch Series 4 maintains the current 18-hour battery life, or six hours when using GPS tracking.The news comes two days after Qualcomm announced an updated smartwatch chipset, significantly extending battery life and supporting four Cortex-A7 cores.A new accelerometer/gyroscope samples motion eight times faster with twice the dynamic range. That enables the device to detect a fall and make an emergency call if it detects no motion for a minute after the event.The Series 4 can pack eight items of data on its expanded 40- to 44-mm display. (Image: Apple)Apple added an electrical sensor in the device’s crown that can generate an electrocardiogram from contact for 30 seconds with a finger. The work won some level of FDA certification but appears to fall below medical-grade accuracy given Apple’s description of it as “similar to a one-lead ECG.”The Series 4 uses 40- and 44-mm curved displays, about a third larger than Apple’s existing devices. The curved displays fit up to eight pieces of information on a single display, letting users configure a wide variety of custom screens.The smartwatches will be available later this month for $499 for versions supporting LTE and $399 for ones using GPS. Apple will discount older Series 3 watches to $279.Both Watch OS 5 and iOS 12 will be available on Sept. 17.“Apple was founded to make the computer more personal, and we’ve taken this mission further than anyone could imagine,” said Cook, noting that the company will ship its three-billionth iOS device soon.“Even though all of the specs and even product names had been leaked, we didn’t know about some of the specific software work that they had to do; things like automatic fall recognition on the watch or the Smart HDR feature on the iPhone,” said Bob O’Donnell, president of Technalysis Research, LLC. “I think these are great examples of the kinds of automatic intelligence features that machine learning will start to enable more of in the future.”

Key word：

Apple

Release time：2018-09-13 00:00 reading：1094 Continue reading>>

Broadcom to Help Design Wave’s 7<span style='color:red'>-nm</span> AI Chip

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Broadcom to Help Design Wave’s 7-nm AI Chip

Wave Computing has set its sights on becoming the first AI startup to develop and deploy a 7-nm AI processor in its AI systems.EE Times has learned that Wave has snagged Broadcom Inc. as an ASIC designer for the new 7-nm project. The two companies will collaborate on development of Wave’s next-generation Dataflow Processing Unit (DPU) by using Taiwan Semiconductor Manufacturing Co.’s 7-nm process node.The new 7-nm DPU — scheduled for delivery by Broadcom at an undisclosed date — will be “designed into our own AI system,” confirmed Wave’s CEO, Derek Meyer. He added that the same chip may become available to others “if there is a market demand.”“Wave is hoping to get a jump on the startup competition with a 7-nm part,” observed Kevin Krewell, principal analyst at Tirias Research. “Most startups don’t have the expertise to build a 7-nm part just yet.” He explained that Broadcom’s involvement made this possible. Broadcom, he noted, “does have more senior ASIC circuit design experience through the acquisition of LSI Logic.”Wave’s current-generation DPU is based on a 16-nm process design.“Among our peers who are designing a new breed of AI accelerators, we will be the first to have access to 7-nm physical IP — such as 56-Gbps and 112-Gbps SerDes — thanks to Broadcom,” noted Meyer. Broadcom is “instrumental to bringing this 7-nm project to fruition,” he explained, thanks to “their industry-leading design platform, productization skills, and proven 7-nm IPs.”Wave’s current-generation DPU based on 16-nm process node was designed by Wave’s employees with the help of contractors. As for the 7-nm DPU, Meyer said, “Between Broadcom and Wave, we have sketched out skills and resources that will be necessary to both front-end and back-end [of the ASIC] designs. We devised our plans for collaboration accordingly.”The joint 7-nm project has been up and running for several months. Broadcom will manage physical delivery of the 7-nm chip. Despite the complexity of 7-nm designs, Meyer said, “I am confident that Broadcom will deliver the first-time right chip.” Wave, however, declined to comment on when its 7-nm DPU will become available.What’s in the 7-nm DPU?Wave did not reveal the architecture of its 7-nm DPU, either.Meyer, however, explained that the new chip will be “based on the data flow architecture.” It will be the first DPU featuring “64-bit MIPS multithreaded CPU.” Wave acquired MIPS in June.Meyer also indicated that Wave’s 7-nm chip will come with “new features in memory,” but he refrained from disclosing what exactly those features are.MIPS’s multithreading technology will play a key role in the new-generation DPU, according to Meyer. In Wave’s dataflow processing, “when we load, unload, and reload data for machine-learning agents, hardware multithreading architecture is effective.” MIPS’s cache coherence is another positive for Wave’s new DPU. “Because our DPU is 64-bit, it only makes sense that both MIPS and DPU talk to the same memory in 64-bit address space,” he said.Asked about Wave’s new features in memory, Krewell said, “Wave’s present chip uses Micron’s Hybrid Memory Cube. And I believe Wave will move to high-bandwidth memory (HBM) in future chips.” He added, “There’s a much better roadmap for HBM. The changing memory architecture will have an impact on the overall system architecture.”Karl Freund, senior analyst at Moor Insights & Strategy, concurred. He said, “For memory, I suspect they will abandon the Hybrid Memory Cube and adopt high-bandwidth memory, which is more cost-effective.”During the interview, Meyer boasted that the new 7-nm DPU should be able to offer 10 times the performance of the company’s current chip.“Remember, we separated the clocks from our chips” in the DPU architecture, he said. Noting that going back and forth to a host creates a bottleneck, he explained that in DPU, an embedded microcontroller loads instructions, cutting down on power and latency wasted by traditional accelerators. “We can take advantage of that capacity available for transistors on the 7-nm chip to increase the performance.”Krewell remained a little skeptical. “As to whether Wave can make a 10x leap, that’s a long reach.” He said, “It depends on how machine-learning performance is measured … and whether Derek [Meyer] was talking training or inference.” He added, “There are a lot of changes going on in inference, with lower-precision (8-bit and below) algorithms being deployed. Training performance is heavily memory-architecture- dependent.”He acknowledged, “But I don’t know the details of what Wave has planned.”

Key word：

AI,Broadcom,Wave

Release time：2018-08-02 00:00 reading：3298 Continue reading>>

TSMC 7<span style='color:red'>-nm</span> Process Experiencing Heavy Market Demand

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TSMC 7-nm Process Experiencing Heavy Market Demand

Taiwan Semiconductor Manufacturing Company, Limited (TSMC) last Thursday at a legal briefing stated that their 7-nm chip process has already gone into mass production. They estimate that during the third quarter it will account for 10% of their revenue and then increase to account for 20% of their revenue in the fourth quarter.TSMC CEO and Vice Chairman C.C. Wei stated that currently 7-nm has already gone into mass production and can be used in servers, AP, CPU, and GPU; furthermore, it is expected to contribute to 10% of TSMC’s revenue. He also pointed out that increased demand for high-speed computers and high-end mobile phones will be the main sources of growth in the third quarter.In addition, the design for EUV equipment which uses 7 + nm was also finalized this month, and they expect to finalize more designs at the end of this year with the processes formally going into mass production in the second quarter of 2019. Following that, 5-nm processes will also be introduced for EUV.

Key word：

TSMC

Release time：2018-07-25 00:00 reading：1002 Continue reading>>

Cadence, Imec Disclose 3<span style='color:red'>-nm</span> Effort

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Cadence, Imec Disclose 3-nm Effort

　　SAN JOSE, Calif. — Cadence Design Systems and the Imec research institute disclosed that they are working toward a 3-nm tapeout of an unnamed 64-bit processor. The effort aims to produce a working chip later this year using a combination of extreme ultraviolet (EUV) and immersion lithography.　　So far, Cadence and Imec have created and validated GDS files using a modified Cadence tool flow. It is based on a metal stack using a 21-nm routing pitch and a 42-nm contacted poly pitch created with data from a metal layer made in an earlier experiment.　　Imec is starting work on the masks and lithography, initially aiming to use double-patterning EUV and self-aligned quadruple patterning (SAQP) immersion processes. Over time, Imec hopes to optimize the process to use a single pass in the EUV scanner. Ultimately, fabs may migrate to a planned high-numerical-aperture version of today’s EUV systems to make 3-nm chips.　　The 3-nm node is expected to be in production as early as 2023. TSMC announced in October plans for a 3-nm fab in Taiwan, later adding that it could be built by 2022. Cadence and Imec have been collaborating on research in the area for two years as an extension of past efforts on 5-nm devices.　　“We made improvements in our digital implementation flow to address the finer routing geometry … there definitely will be some new design rules at 3 nm,” said Rod Metcalfe, a product management group director at Cadence, declining to provide specifics. “We needed to get some early visibility so when our customers do 3 nm in a few years, EDA tools will be well-defined.”　　Besides the finer features, the first two layers of 3-nm chips may use different metalization techniques and metals such as cobalt, said Ryoung-han Kim, an R&D group manager at Imec. The node is also expected to use new transistor designs such as nanowires or nanosheets rather than the FinFETs used in today’s 16-nm and finer processes.　　“Our work on the test chip has enabled interconnect variation to be measured and improved and the 3-nm manufacturing process to be validated,” said An Steegen, executive vice president for semiconductor technology and systems at Imec, in a press statement.　　The research uses Cadence Innovus Implementation System and Genus Synthesis tools. Imec is using a custom 3-nm cell library and a TRIM metal flow. The announcement of their collaboration comes one day after Imec detailed findings of random defectsimpacting 5-nm designs.

Key word：

Cadence

Release time：2018-03-01 00:00 reading：1089 Continue reading>>

EUV Defects Cited in 5<span style='color:red'>-nm</span> Node

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EUV Defects Cited in 5-nm Node

　　SAN JOSE, Calif. — Researchers reported random defects appearing in extreme ultraviolet (EUV) lithography at 5-nm nodes. They are applying an array of techniques to eliminate them but, so far, see no clear solution.　　The news comes as Globalfoundries, Samsung, and TSMC are racing to rev EUV systems up to high availability with 250-W light sources for 7-nm production next year. The defects show that there’s no panacea for the increasing costs and complexity of making semiconductors.　　The latest EUV scanners can print the 20-nm-and-larger critical dimensions that foundries plan at 7 nm, said Greg McIntyre, a patterning expert from the Imec research institute in Belgium. However, their ability to make finer lines and holes is unclear, he said in a talk at the SPIE Advanced Lithography conference here.　　Optimists such as McIntyre believe that a basket of solutions will emerge for the so-called stochastic effects. Some skeptics see the results as one more reason to doubt that the expensive and long-delayed EUV systems will become mainstream tools for chipmakers.　　A retired Intel lithographer predicted that engineers will be able to create 5-nm and even 3-nm devices by using two and three passes with an EUV stepper. But a rising tide of chip defects ultimately will drive engineers to new, fault-tolerant processor architectures such as neural networks, said Yan Borovodsky in a keynote at the event.　　The latest defects are cropping up at critical dimensions around 15 nm needed to make 5-nm chips for foundry processes targeting 2020. EUV maker ASML is preparing a next-generation EUV system for printing finer features, but those systems won’t be available until about 2024, it said at the event last year.　　The random defects take many forms. Some are imperfectly made holes; others are tears in lines or shorts where two lines or two holes meet. Given their tiny dimensions, researchers sometimes spend days just to find them.　　McIntyre outlined the challenges finding and eliminating the errors. For example, some researchers are proposing this week a standard way to measure the roughness of lines, one key to understanding the defects.　　Another issue is that it’s unclear exactly what happens to resist materials when hit with EUV light. “It’s still unknown how many electrons are generated and what kinds of chemistries are created … we’re a little ways from a full understanding of the physics, so we’re doing more experiments,” said McIntyre, noting that researchers have tested as many as 350 combinations of resists and process steps.　　“Manufacturing guys will get beat up incredibly over yield loss … if I was going to be responsible for this, I’d say it’s time to retire,” quipped one veteran lithographer during a Q&A session about the 5-nm defects.　　A Globalfoundries technologist provided a more upbeat but sober assessment in another keynote. “It’s been a lot of hard work, and there’s a lot more hard work to come,” said George Gomba, a vice president of research at GF, recalling a nearly 30-year history of work on EUV.　　Today’s NXE 3400 systems are “not meeting some roadmap conditions we desire, so there is still some uncertainty [at 7 nm]. If we do not make productivity and availability improvements, we may only be able to use EUV for the most aggressive processors.”　　Gomba noted that the random defects at 5 nm include subtle 3D breaks and tears such as notches in lines. He also called for more work on so-called actinic systems that inspect EUV masks before lithographers cover them with protective pellicles.　　“To get full use of EUV, we will need actinic inspection systems [still in development], maybe complementing e-beam mask inspection systems” that are available today.　　In an interview, Borodovsky said that another factor that may be contributing to the 5-nm defects is a lack of homogeneity in the current EUV resist materials. Separately, he said that he supports work on direct e-beam writers because the complex phase-shift masks that EUV uses ultimately will balloon to eight times the price of today’s immersion masks.　　Multibeam, a company formed by Lam Research founder David Lam, recently snagged $35 million in government funding for his e-beam technology. He hopes to have commercial systems in 2.5 years for niche applications, but versions suitable for high-volume manufacturing will take much longer, said Lam.　　By 2024, defects could become so widespread that conventional processors will not be able to be made in leading-edge processes, said Borodovsky. Experimental chips using memory arrays with embedded computing elements could be more fault-tolerant, citingIBM’s True North chip and work by HP Labs with memristors.

Key word：

EUV

Release time：2018-02-28 00:00 reading：1153 Continue reading>>

EUV, 7<span style='color:red'>-nm</span> Roadmaps Detailed

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EUV, 7-nm Roadmaps Detailed

　　Extreme ultraviolet lithography (EUV) is set to enable 10-nm and 7-nm process nodes over the next few years, but significant work is still needed on photoresists to enable 5-nm chips, according to an analysis released at the Industry Strategy Symposium here.　　At the same time, EUV maker ASML announced that it shipped 10 EUV systems last year and will ship 20 to 22 more this year. The systems will have, or at least support, a 250-W laser light source needed to produce 125 wafers/hour.　　“The main pieces for EUV at 7 nm are in place, and we will see some volume of wafers this year … but photoresist defects are still an order of magnitude too high for 5 nm,” said Scotten Jones, president of IC Knowledge.　　The new and expensive systems, in development more than 20 years, help make the fine features needed for next-generation chips and reduce the time required to make them. They will first be used on logic chips such as microprocessors and later applied to DRAMs but are not needed by today’s 3D NAND flash chips, said Scotten.　　“EUV provides a tremendous reduction in cycle time and edge placement errors … but not much cost reduction, at least initially. There are so many other benefits that even if the cost is neutral, it still makes sense.”　　Jones expects that ASML will ship another 70 systems in 2019–2020. That’s enough to support production nodes that he detailed in the works at Globalfoundries, Intel, Samsung, and TSMC.　　ASML has plans in place to increase uptime of the systems from about 75% today to 90%, a top concern for lithographers, said Jones. In addition, he expressed confidence that the company will release in time a pellicle needed to protect some EUV wafers from contamination.　　To enable resists for 5 nm, “we have 12 to 18 months to make a big improvement. The industry will run lots of wafers next year, and that will help,” said Jones, estimating that fabs will make nearly 1 million EUV wafers in 2019, and 3.4 million by 2021.　　ASML aims to boost the 145 wafers/hour throughput that it can get with its 250-W light source to 155 w/h in 2020. It has demonstrated a 375-W light source working in the lab, said Peter Jenkins, ASML’s vice president for corporate strategy and marketing, in a talk here.　　The company’s pellicle passes through 83% of light today and withstands a 245-W light source over 7,000 wafer exposures. However, the most aggressive 7-nm nodes need a 90% transmission used with a 250-W or greater light source.　　One of the most interesting parts of Jones’ talk was a detailed analysis of 10-, 7-, and 5-nm nodes. TSMC qualified last fall a 7-nm process that is ramping now using existing optical steppers. Globalfoundries will ramp a similar process later this year, he said.　　Both companies plan to ramp early next year a second-generation 7-nm process using EUV to make contacts and vias, reducing 15 optical layers to five EUV layers. The process does not provide a shrink, but it shortens cycle times and does not need a pellicle.　　GF announced last June its 2019 plan for 7 nm with EUV. “TSMC has privately told customers that they will do this, too,” said Jones.　　Chipmakers will probably have to use 30-ml/cm2 doses of resists, higher than the 20 ml/cm2that they target. They also will likely have to use e-beam systems to insect masks for defects rather than more accurate actinic systems still in the works that look for defects using the same 13.5-mm wavelength as the EUV systems, said Jones.　　In addition to the work with cuts and vias, GF, Samsung, and TSMC plan 7-nm variants that use EUV with a pellicle to make a first metal layer. These processes will provide a shrink and reduce 23 optical layers to nine EUV layers.　　This is the approach that Samsung will use for its first 7-nm node, called 7LPP, due early next year. TSMC will call its version 7FF+ and ramp it in mid-2019, and GF will follow with its 7LP+ late next year, said Jones.　　The 10-nm process that Intel is currently ramping using optical steppers offers similar density to what its rivals plan with their best 7-nm variants, said Jones. He expects that Intel will adopt EUV for a 10-nm+ upgrade in 2019.　　Samsung and TSMC are already talking about 5-nm processes that could be available before the end of 2019. They could be the first to use EUV for 1D metal layers. The processes could use EUV to reduce up to five cut masks for FinFETs down to one cut mask if better resists emerge, he said.　　Separately, Jenkins said that ASML completed the optics design for its follow on EUV systems supporting a high numerical aperture, and its overall design is “well along.” The company announced in late 2016 plans for the system that should be in volume production in 2024.　　Although EUV is a big milestone for enabling the semiconductor industry to make smaller chips, it is not expected to disrupt existing markets for chipmaking equipment and gear. Fabs will continue to need lots of existing capital equipment and supplies in tandem with EUV for future process nodes, said Jones.

Key word：

EUV, 7-nm Roadmaps

Release time：2018-01-19 00:00 reading：1111 Continue reading>>

TSMC Aims to Build World’s First 3<span style='color:red'>-nm</span> Fab

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TSMC Aims to Build World’s First 3-nm Fab

　　Taiwan Semiconductor Manufacturing Co. (TSMC) will build the world’s first 3-nm fab in the Tainan Science Park in southern Taiwan, where the company does the bulk of its manufacturing.　　The announcement lays to rest speculation that the company might build its next chip facility in the U.S., attracted by incentives offered by the administration of President Donald Trump to bring more manufacturing to America.　　About a year ago, TSMC said it planned to build its next fab at the 5-nm to 3-nm technology node as early as 2022. The more recent one-paragraph announcement from TSMC on Sept. 29 didn’t provide a timeframe for the opening of the 3-nm fab.　　“TSMC recognizes and is grateful for the (Taiwan) government’s clear commitments to resolve any issues, including land, water, electricity and environmental protection,” the statement said.　　TSMC previously estimated it would need 50 to 80 hectares (123 to 198 acres) of land for an investment worth about NT$500 billion ($15.7 billion). The company’s earlier 2022 timeframe for the fab takes into account potentially unanticipated delays in construction. Some of TSMC’s recent projects in Taiwan have been set back by as much as a year by public hearings on environmental impact.　　TSMC has also faced shortages of water and power in Taiwan, where the company does most of its production.　　Process Leaders　　TSMC, Samsung and Intel have been in a tight race to lead process technology development and grab profits from fabless customers such as Apple and Qualcomm.　　Earlier this year, TSMC logged its first revenue from 10nm products, trailing Samsung, its main rival in the foundry business, by nearly four months.　　TSMC said its 7-nm yield is ahead of schedule and it expects a fast ramp in 2018. The company plans to insert several extreme ultraviolet (EUV) layers at 7 nm, but declined to provide details. The company plans to offer a 7-nm plus node that it expects will allow customers easy migration from 7 nm.　　TSMC has also said its 5-nm roadmap is on track for a launch in the first quarter of 2019.

Key word：

TSMC,3-nm Fab

Release time：2017-10-09 00:00 reading：1327 Continue reading>>

TMSC, ARM, Xilinx, Cadence Partner on 7<span style='color:red'>-nm</span> Process

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TMSC, ARM, Xilinx, Cadence Partner on 7-nm Process

　　Xilinx, ARM, Cadence, and TSMC have announced a partnership to build a test chip in 7-nm FinFET process technology for delivery next year that promises to speed data center applications.　　The chip will be the first demonstration in silicon of Cache Coherent Interconnect for Accelerators (CCIX) enabling multi-core high-performance ARM CPUs working via a coherent fabric with off-chip FPGA accelerators, said the partners in a press statement.　　Accelerating applications in data centers is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, and network processing benefit from acceleration engines that move data effectively among various system components.　　CCIX will allow components to access and process data irrespective of where it resides without the need for complex programming environments. CCIX will use existing server interconnect infrastructure and deliver higher bandwidth, lower latency, and cache coherent access to shared memory.　　This will result in a significant improvement in the effectiveness of accelerators as well as overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership of acceleration systems.　　The test chip, implemented on TSMC’s 7-nm process, will be based on the latest ARM DynamIQ technology, CMN-600 coherent on-chip bus, and foundation IP.　　“With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager of ARM's Infrastructure Group. “The test chip will not only demonstrate how the latest ARM technology with coherent multichip accelerators can scale across the data center but reinforces our commitment to solving the challenge of accessing data quickly and easily.”　　To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe-4/3) IP solution (controller and PHY), DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip.　　The test chip provides connectivity to Xilinx’s 16-nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.　　“Our Virtex UltraScale+ HBM family is built using TSMC’s third-generation CoWoS technology, which is now the industry standard assembly for HBM integration and cache-coherent acceleration with CCIX," said Victor Peng, chief operating officer at Xilinx.　　The test chip will tape out early in the first quarter of 2018, with silicon availability expected in the second half of 2018.　　“By building an ecosystem for high-performance computing with our collaboration partners, we will enable our customers to quickly deploy innovative new architectures at 7 nm and other advanced nodes for these growing data center applications,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “The CCIX industry standard will help drive the next generation of interconnect that provides the high-performance cache coherency that the market is demanding.”　　Artificial intelligence and deep learning will significantly impact industries including media, consumer electronics, and healthcare, according to Cliff Hou, TSMC vice president, Research & Development/Design and Technology Platform.　　“TSMC’s most advanced 7-nm FinFET process technology provides high-performance and low-power benefits that satisfy distinct product requirements for High-Performance Computing applications targeting these markets,” said Hou.

Key word：

TMSC, ARM, Xilinx, Cadence,-nm

Release time：2017-09-12 00:00 reading：3277 Continue reading>>

model	brand	Quote
TL431ACLPR	Texas Instruments
RB751G-40T2R	ROHM Semiconductor
CDZVT2R20B	ROHM Semiconductor
BD71847AMWV-E2	ROHM Semiconductor
MC33074DR2G	onsemi

model	brand	To snap up
STM32F429IGT6	STMicroelectronics
IPZ40N04S5L4R8ATMA1	Infineon Technologies
BU33JA2MNVX-CTL	ROHM Semiconductor
TPS63050YFFR	Texas Instruments
BP3621	ROHM Semiconductor
ESR03EZPJ151	ROHM Semiconductor

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